Imperial College London
Alternate

ProfessorChristos-SavvasBouganis

Faculty of Engineering, Department of Electrical and Electronic Engineering

Professor of Intelligent Digital Systems
 
 
 
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Contact

 

+44 (0)20 7594 6144christos-savvas.bouganis Website

 
 
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Location

 

904Electrical EngineeringSouth Kensington Campus

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Summary

 

Publications

Citation

BibTex format

@article{Venieris:2019:10.1109/TNNLS.2018.2844093,
author = {Venieris, S and Bouganis, C},
doi = {10.1109/TNNLS.2018.2844093},
journal = {IEEE Transactions on Neural Networks and Learning Systems},
pages = {326--342},
title = {fpgaConvNet: mapping regular and irregular convolutional neural networks on FPGAs},
url = {http://dx.doi.org/10.1109/TNNLS.2018.2844093},
volume = {30},
year = {2019}
}
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RIS format (EndNote, RefMan)

TY  - JOUR
AB  - Since neural networks renaissance, convolutional neural networks (ConvNets) have demonstrated a state-of-the-art performance in several emerging artificial intelligence tasks. The deployment of ConvNets in real-life applications requires power-efficient designs that meet the application-level performance needs. In this context, field-programmable gate arrays (FPGAs) can provide a potential platform that can be tailored to application-specific requirements. However, with the complexity of ConvNet models increasing rapidly, the ConvNet-to-FPGA design space becomes prohibitively large. This paper presents fpgaConvNet, an end-to-end framework for the optimized mapping of ConvNets on FPGAs. The proposed framework comprises an automated design methodology based on the synchronous dataflow (SDF) paradigm and defines a set of SDF transformations in order to efficiently navigate the architectural design space. By proposing a systematic multiobjective optimization formulation, the presented framework is able to generate hardware designs that are cooptimized for the ConvNet workload, the target device, and the application's performance metric of interest. Quantitative evaluation shows that the proposed methodology yields hardware designs that improve the performance by up to 6.65x over highly optimized graphics processing unit designs for the same power constraints and achieve up to 2.94x higher performance density compared with the state-of-the-art FPGA-based ConvNet architectures.
AU  - Venieris,S
AU  - Bouganis,C
DO  - 10.1109/TNNLS.2018.2844093
EP  - 342
PY  - 2019///
SN  - 2162-2388
SP  - 326
TI  - fpgaConvNet: mapping regular and irregular convolutional neural networks on FPGAs
T2  - IEEE Transactions on Neural Networks and Learning Systems
UR  - http://dx.doi.org/10.1109/TNNLS.2018.2844093
UR  - https://ieeexplore.ieee.org/document/8401525
UR  - http://hdl.handle.net/10044/1/60521
VL  - 30
ER  -
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