Imperial College London

ProfessorChristos-SavvasBouganis

Faculty of EngineeringDepartment of Electrical and Electronic Engineering

Professor of Intelligent Digital Systems
 
 
 
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Contact

 

+44 (0)20 7594 6144christos-savvas.bouganis Website

 
 
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Location

 

904Electrical EngineeringSouth Kensington Campus

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Summary

 

Publications

Citation

BibTex format

@inproceedings{Venieris:2018,
author = {Venieris, SI and Bouganis, C-S},
title = {f-CNNx: a toolflow for mapping multiple convolutional neural networks on FPGAs},
url = {http://hdl.handle.net/10044/1/60780},
year = {2018}
}

RIS format (EndNote, RefMan)

TY  - CPAPER
AB - The predictive power of Convolutional Neural Networks (CNNs) has been an integral factor for emerging latency-sensitive applications, such as autonomous drones and vehicles. Such systems employ multiple CNNs, each one trained for a particular task. The efficient mapping of multiple CNNs on a single FPGA device is a challenging task as the allocation of compute resources and external memory bandwidth needs to be optimised at design time. This paper proposes f-CNNx, an automated toolflow for the optimised mapping of multiple CNNs on FPGAs, comprising a novel multi-CNN hardware architecture together with an automated design space exploration method that considers the user-specified performance requirements for each model to allocate compute resources and generate a synthesisable accelerator. Moreover, f-CNNx employs a novel scheduling algorithm that alleviates the limitations of the memory bandwidth contention between CNNs and sustains the high utilisation of the architecture. Experimental evaluation shows that f-CNNx's designs outperform contention-unaware FPGA mappings by up to 50% and deliver up to 6.8x higher performance-per-Watt over highly optimised GPU designs for multi-CNN systems.
AU - Venieris,SI
AU - Bouganis,C-S
PY - 2018///
TI - f-CNNx: a toolflow for mapping multiple convolutional neural networks on FPGAs
UR - http://hdl.handle.net/10044/1/60780
ER -