Imperial College London
Alternate

ProfessorChristos-SavvasBouganis

Faculty of Engineering, Department of Electrical and Electronic Engineering

Professor of Intelligent Digital Systems
 
 
 
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Contact

 

+44 (0)20 7594 6144christos-savvas.bouganis Website

 
 
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Location

 

904Electrical EngineeringSouth Kensington Campus

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Summary

 

Publications

Citation

BibTex format

@inproceedings{Yu:2020:10.1007/978-3-030-44534-8_25,
author = {Yu, Z and Bouganis, C-S},
doi = {10.1007/978-3-030-44534-8_25},
pages = {330--344},
publisher = {Springer International Publishing},
title = {A parameterisable FPGA-tailored architecture for YOLOv3-Tiny},
url = {http://dx.doi.org/10.1007/978-3-030-44534-8_25},
year = {2020}
}
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RIS format (EndNote, RefMan)

TY  - CPAPER
AB  - Object detection is the task of detecting the position of objects in an image or video as well as their corresponding class. The current state of the art approach that achieves the highest performance (i.e. fps) without significant penalty in accuracy of detection is the YOLO framework, and more specifically its latest version YOLOv3. When embedded systems are targeted for deployment, YOLOv3-tiny, a lightweight version of YOLOv3, is usually adopted. The presented work is the first to implement a parameterised FPGA-tailored architecture specifically for YOLOv3-tiny. The architecture is optimised for latency-sensitive applications, and is able to be deployed in low-end devices with stringent resource constraints. Experiments demonstrate that when a low-end FPGA device is targeted, the proposed architecture achieves a 290x improvement in latency, compared to the hard core processor of the device, achieving at the same time a reduction in mAP of 2.5 pp (30.9% vs 33.4%) compared to the original model. The presented work opens the way for low-latency object detection on low-end FPGA devices.
AU  - Yu,Z
AU  - Bouganis,C-S
DO  - 10.1007/978-3-030-44534-8_25
EP  - 344
PB  - Springer International Publishing
PY  - 2020///
SN  - 0302-9743
SP  - 330
TI  - A parameterisable FPGA-tailored architecture for YOLOv3-Tiny
UR  - http://dx.doi.org/10.1007/978-3-030-44534-8_25
UR  - https://link.springer.com/chapter/10.1007/978-3-030-44534-8_25
UR  - http://hdl.handle.net/10044/1/103452
ER  -
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