Imperial College London

ProfessorChristos-SavvasBouganis

Faculty of EngineeringDepartment of Electrical and Electronic Engineering

Professor of Intelligent Digital Systems
 
 
 
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Contact

 

+44 (0)20 7594 6144christos-savvas.bouganis Website

 
 
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Location

 

904Electrical EngineeringSouth Kensington Campus

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Summary

 

Publications

Citation

BibTex format

@unpublished{Vink:2020,
author = {Vink, DA and Rajagopal, A and Venieris, SI and Bouganis, C-S},
publisher = {arXiv},
title = {Caffe barista: brewing caffe with FPGAs in the training loop},
url = {http://arxiv.org/abs/2006.13829v1},
year = {2020}
}

RIS format (EndNote, RefMan)

TY  - UNPB
AB - As the complexity of deep learning (DL) models increases, their computerequirements increase accordingly. Deploying a Convolutional Neural Network(CNN) involves two phases: training and inference. With the inference tasktypically taking place on resource-constrained devices, a lot of research hasexplored the field of low-power inference on custom hardware accelerators. Onthe other hand, training is both more compute- and memory-intensive and isprimarily performed on power-hungry GPUs in large-scale data centres. CNNtraining on FPGAs is a nascent field of research. This is primarily due to thelack of tools to easily prototype and deploy various hardware and/oralgorithmic techniques for power-efficient CNN training. This work presentsBarista, an automated toolflow that provides seamless integration of FPGAs intothe training of CNNs within the popular deep learning framework Caffe. To thebest of our knowledge, this is the only tool that allows for such versatile andrapid deployment of hardware and algorithms for the FPGA-based training ofCNNs, providing the necessary infrastructure for further research anddevelopment.
AU - Vink,DA
AU - Rajagopal,A
AU - Venieris,SI
AU - Bouganis,C-S
PB - arXiv
PY - 2020///
TI - Caffe barista: brewing caffe with FPGAs in the training loop
UR - http://arxiv.org/abs/2006.13829v1
UR - http://hdl.handle.net/10044/1/80450
ER -