Imperial College London
Alternate

ProfessorChristos-SavvasBouganis

Faculty of Engineering, Department of Electrical and Electronic Engineering

Professor of Intelligent Digital Systems
 
 
 
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Contact

 

+44 (0)20 7594 6144christos-savvas.bouganis Website

 
 
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Location

 

904Electrical EngineeringSouth Kensington Campus

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Summary

 

Publications

Citation

BibTex format

@article{Rosa:2021:10.1016/j.micpro.2021.104334,
author = {Rosa, LDS and Bouganis, C-S and Bonato, V},
doi = {10.1016/j.micpro.2021.104334},
journal = {Microprocessors and Microsystems},
pages = {1--13},
title = {Non-iterative SDC modulo scheduling for high-level synthesis},
url = {http://dx.doi.org/10.1016/j.micpro.2021.104334},
volume = {86},
year = {2021}
}
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RIS format (EndNote, RefMan)

TY  - JOUR
AB  - High-level synthesis is a powerful tool for increasing productivity in digital hardware design. However, as digital systems become larger and more complex, designers have to consider an increased number of optimizations and directives offered by high-level synthesis tools to control the hardware generation process. One of the most explored optimizations is loop pipelining due to its impact on hardware throughput and resources. Nevertheless, the modulo scheduling algorithms used at resource-constrained loop pipelining are computationally expensive, and their application through the whole design space is often non-viable. Current state-of-the-art approaches rely on solving multiple optimization problems in polynomial time, or on solving one optimization problem in exponential time. This work proposes a novel data-flow-based approach, where exactly two optimization problems of polynomial time complexity are solved, leading to significant reductions on computation time for generating a single loop pipeline. Results indicate that, even for complex loops, the proposed method generates high-quality designs, comparable to the ones produced by existing state-of-the-art methods, achieving a reduction on the design-space exploration time by
AU  - Rosa,LDS
AU  - Bouganis,C-S
AU  - Bonato,V
DO  - 10.1016/j.micpro.2021.104334
EP  - 13
PY  - 2021///
SN  - 0141-9331
SP  - 1
TI  - Non-iterative SDC modulo scheduling for high-level synthesis
T2  - Microprocessors and Microsystems
UR  - http://dx.doi.org/10.1016/j.micpro.2021.104334
UR  - http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000704988000001&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=1ba7043ffcc86c417c072aa74d649202
UR  - https://www.sciencedirect.com/science/article/pii/S0141933121004932?via%3Dihub
UR  - http://hdl.handle.net/10044/1/92352
VL  - 86
ER  -
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