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BibTex format

@inproceedings{Vavouras:2017:10.1109/ReConFig.2016.7857154,
author = {Vavouras, M and Bouganis, C-S},
doi = {10.1109/ReConFig.2016.7857154},
publisher = {IEEE},
title = {Area-driven partial reconfiguration for SEU mitigation on SRAM-based FPGAs},
url = {http://dx.doi.org/10.1109/ReConFig.2016.7857154},
year = {2017}
}

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TY  - CPAPER
AB  - This paper presents an area-driven Field-Programmable Gate Array (FPGA) scrubbing technique based on partial reconfiguration for Single Event Upset (SEU) mitigation. The proposed method is compared with existing techniques such as blind and on-demand scrubbing on a novel SEU mitigation framework implemented on the ZYNQ platform, supporting various SEU and scrubbing rates. A design space exploration on the availability versus data transfers from a Double Data Rate Type 3 (DDR3) memory, shows that our approach outperforms blind scrubbing for a range of availability values when a second order polynomial IP is targeted. A comparison to an existing on-demand scrubbing technique based on Dual Modular Redundancy (DMR) shows that our approach saves up to 46% area for the same case study.
AU  - Vavouras,M
AU  - Bouganis,C-S
DO  - 10.1109/ReConFig.2016.7857154
PB  - IEEE
PY  - 2017///
SN  - 2325-6532
TI  - Area-driven partial reconfiguration for SEU mitigation on SRAM-based FPGAs
UR  - http://dx.doi.org/10.1109/ReConFig.2016.7857154
UR  - http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000400775800012&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=1ba7043ffcc86c417c072aa74d649202
UR  - http://hdl.handle.net/10044/1/54274
ER  -

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ProfessorChristos-SavvasBouganis

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