Hello! I'm David Thomas and am a lecturer in this fine department. I'm part of the Circuits and Systems research group in EEE, which means I'm on level 9 of the EEE building, and more specifically in room 903.
I currently teach three courses:
- Language Processors (EE2-15) : an introduction to automata theory and compiler design, resulting in the creation of a C compiler, taken by EIE students in the second year.
- Computer Architecture (C210=EE2-13) : an introduction to CPU design, taken by both EIE and Computing students in the second year.
- High Performance Computing for Engineers (EE4-63) : tries to get people up and running with practical multi-core and GPU programming, without most of the pain of parallel programming. Currently available to 4th years from EEE, EIE, and the ADIC MSc programme
I am also the course director for the Electronic and Information Engineering degree course (previously called Information Systems Engineering (ISE)).
Within the Circuits and Systems group I run the Accelerated Numerics research group. This group mostly explores ways in which accelerators such as FPGAs and GPUs can be used to accelerate compute-intensive numerical calculations, such as in computational finance (though more recently this has started to encompass data-oriented processing as well). My particular interest is in trying to rethink algorithms and applications to take advantage of hardware, rather than trying to force existing software algorithms and C code into an FPGA.
In 2016 I am hosting ASAP 2016
Thomas D, Templatised soft floating-point for High-Level Synthesis, The 27th IEEE International Symposium On Field-Programmable Custom Computing Machines, IEEE
Faissole F, Constantinides GA, Thomas D, 2019, Formalizing Loop-carried Dependencies in Coq for High-Level Synthesis, 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), IEEE COMPUTER SOC, Pages:315-315
et al., 2019, A type-safe arbitrary precision arithmetic portability layer for HLS tools, 10th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART), ASSOC COMPUTING MACHINERY
et al., 2019, Accelerating Position-Aware Top-k ListNet for Ranking under Custom Precision Regimes, 29th International Conference on Field-Programmable Logic and Applications (FPL), IEEE, Pages:81-87, ISSN:1946-1488
Naylor M, Moore SW, Thomas D, 2019, Tinsel: a manythread overlay for FPGA clusters, 29th International Conference on Field-Programmable Logic and Applications (FPL), IEEE, Pages:375-383, ISSN:1946-1488