Imperial College London

ProfessorEricKerrigan

Faculty of EngineeringDepartment of Electrical and Electronic Engineering

Professor of Control and Optimization
 
 
 
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Contact

 

+44 (0)20 7594 6343e.kerrigan Website

 
 
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Assistant

 

Mrs Raluca Reynolds +44 (0)20 7594 6281

 
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Location

 

1114Electrical EngineeringSouth Kensington Campus

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Summary

 

Publications

Citation

BibTex format

@inproceedings{Biggs:2022,
author = {Biggs, B and McInerney, I and Kerrigan, EC and Constantinides, GA},
title = {High-level synthesis using the Julia language},
url = {http://arxiv.org/abs/2201.11522v1},
year = {2022}
}

RIS format (EndNote, RefMan)

TY  - CPAPER
AB - The growing proliferation of FPGAs and High-level Synthesis (HLS) tools hasled to a large interest in designing hardware accelerators for complexoperations and algorithms. However, existing HLS toolflows typically require asignificant amount of user knowledge or training to be effective in bothindustrial and research applications. In this paper, we propose using the Julialanguage as the basis for an HLS tool. The Julia HLS tool aims to decrease thebarrier to entry for hardware acceleration by taking advantage of thereadability of the Julia language and by allowing the use of the existing largelibrary of standard mathematical functions written in Julia. We present aprototype Julia HLS tool, written in Julia, that transforms Julia code to VHDL.We highlight how features of Julia and its compiler simplified the creation ofthis tool, and we discuss potential directions for future work.
AU - Biggs,B
AU - McInerney,I
AU - Kerrigan,EC
AU - Constantinides,GA
PY - 2022///
TI - High-level synthesis using the Julia language
UR - http://arxiv.org/abs/2201.11522v1
UR - http://hdl.handle.net/10044/1/95997
ER -