Imperial College London
Alternate

DrEdwardStott

Faculty of Engineering, Department of Electrical and Electronic Engineering

Senior Teaching Fellow
 
 
 
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Contact

 

+44 (0)20 7594 6314ed.stott

 
 
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Location

 

612Electrical EngineeringSouth Kensington Campus

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Summary

 

Publications

Citation

BibTex format

@inproceedings{Hung:2016:10.1109/FCCM.2016.25,
author = {Hung, E and Davis, JJ and Levine, JM and Stott, EA and Cheung, PYK and Constantinides, GA},
doi = {10.1109/FCCM.2016.25},
pages = {56--63},
publisher = {IEEE},
title = {KAPow: A System Identification Approach to Online Per-Module Power Estimation in FPGA Designs},
url = {http://dx.doi.org/10.1109/FCCM.2016.25},
year = {2016}
}
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RIS format (EndNote, RefMan)

TY  - CPAPER
AB  - In a modern FPGA system-on-chip design, it is often insufficient to simply assess the total power consumption of the entire circuit by design-time estimation or runtime power rail measurement. Instead, to make better runtime decisions, it is desirable to understand the power consumed by each individual module in the system. In this work, we combine board-level power measurements with register-level activity counting to build an online model that produces a breakdown of power consumption within the design. Online model refinement avoids the need for a time-consuming characterisation stage and also allows the model to track long-term changes to operating conditions. Our flow is named KAPow, a (loose) acronym for 'K'ounting Activity for Power estimation, which we show to be accurate, with per-module power estimates as close to +/-5mW of true measurements, and to have low overheads. We also demonstrate an application example in which a per-module power breakdown can be used to determine an efficient mapping of tasks to modules and reduce system-wide power consumption by over 8%.
AU  - Hung,E
AU  - Davis,JJ
AU  - Levine,JM
AU  - Stott,EA
AU  - Cheung,PYK
AU  - Constantinides,GA
DO  - 10.1109/FCCM.2016.25
EP  - 63
PB  - IEEE
PY  - 2016///
SP  - 56
TI  - KAPow: A System Identification Approach to Online Per-Module Power Estimation in FPGA Designs
UR  - http://dx.doi.org/10.1109/FCCM.2016.25
UR  - http://cas.ee.ic.ac.uk/people/gac1/pubs/EddieFCCM16.pdf
UR  - http://ieeexplore.ieee.org/document/7544748/
UR  - http://hdl.handle.net/10044/1/31009
ER  -
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