Imperial College London

DrIanWilliams

Faculty of EngineeringDepartment of Electrical and Electronic Engineering

Research Associate
 
 
 
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Contact

 

i.williams10

 
 
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Location

 

City and Guilds BuildingSouth Kensington Campus

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Summary

 

Publications

Publication Type
Year
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15 results found

Luan S, Williams I, Maslik M, Liu Y, De Carvalho F, Jackson A, Quian Quiroga R, Constandinou Tet al., 2018, Compact Standalone Platform for Neural Recording with Real-Time Spike Sorting and Data Logging, Journal of Neural Engineering, Vol: 15, Pages: 1-21, ISSN: 1741-2552

Objective. Longitudinal observation of single unit neural activity from largenumbers of cortical neurons in awake and mobile animals is often a vital step in studying neural network behaviour and towards the prospect of building effective Brain Machine Interfaces (BMIs). These recordings generate enormous amounts of data for transmission & storage, and typically require o ine processing to tease out the behaviour of individual neurons. Our aim was to create a compact system capable of: 1) reducing the data bandwidth by circa 2 to 3 orders of magnitude (greatly improving battery lifetime and enabling low power wireless transmission in future versions); 2) producing real-time, low-latency, spike sorted data; and 3) long term untethered operation. Approach. We have developed a headstage that operates in two phases. In the short training phase a computer is attached and classic spike sorting is performed to generate templates. In the second phase the system is untethered and performs template matching to create an event driven spike output that is logged to a micro-SD card. To enable validation the system is capable of logging the high bandwidth raw neural signal data as well as the spike sorted data. Main results. The system can successfully record 32 channels of raw neural signal data and/or spike sorted events for well over 24 hours at a time and is robust to power dropouts during battery changes as well as SD card replacement. A 24-hour initial recording in a nonhuman primate M1 showed consistent spike shapes with the expected changes in neural activity during awake behaviour and sleep cycles. Signi cance The presented platform allows neural activity to be unobtrusively monitored and processed in real-time in freely behaving untethered animals { revealing insights that are not attainable through scheduled recording sessions. This system achieves the lowest power per channel to date and provides a robust, low-latency, low-bandwidth and veri able output suitable f

Journal article

Williams I, 2018, Zero mean waveforms for neural stimulation

Biphasic charge balanced waveforms do not minimise faradaic processes at the electrode-electrolyte boundary and do not leave electrodes neutral with respect to the tissue. Superior waveforms for electrode health (and consequently tissue safety) exist and may also offer better performance in terms of power consumption and stimulation effectiveness within charge injection limits. This paper aims to provide intuitive insight into the limitations of biphasic waveforms and presents a simple method for assessing how well other waveforms will perform, as well as methods for designing waveforms to theoretically give zero residual voltage and zero net faradaic charge transfer.

Working paper

Williams I, Rapeaux A, Luan S, Constandinou TGet al., 2018, Waveform Generator

Patent

Williams I, Leene L, Constandinou TG, 2018, Next Generation Neural Interface Electronics, Circuit Design Considerations for Implantable Devices, Editors: Cong, Publisher: River Publishers, Pages: 141-178, ISBN: 978-87-93519-86-2

Book chapter

Liu Y, Luan S, Williams I, Rapeaux A, Constandinou TGet al., 2017, A 64-Channel Versatile Neural Recording SoC with Activity Dependant Data Throughput, IEEE Transactions on Biomedical Circuits and Systems, Vol: 11, Pages: 1344-1355, ISSN: 1932-4545

Modern microtechnology is enabling the channel count of neural recording integrated circuits to scale exponentially. However, the raw data bandwidth of these systems is increasing proportionately, presenting major challenges in terms of power consumption and data transmission (especially for wireless systems). This paper presents a system that exploits the sparse nature of neural signals to address these challenges and provides a reconfigurable low-bandwidth event-driven output. Specifically, we present a novel 64-channel low noise (2.1μVrms, low power (23μW per analogue channel) neural recording system-on-chip (SoC). This features individually-configurable channels, 10-bit analogue-to-digital conversion, digital filtering, spike detection, and an event-driven output. Each channel's gain, bandwidth & sampling rate settings can be independently configured to extract Local Field Potentials (LFPs) at a low data-rate and/or Action Potentials (APs) at a higher data rate. The sampled data is streamed through an SRAM buffer that supports additional on-chip processing such as digital filtering and spike detection. Real-time spike detection can achieve ~2 orders of magnitude data reduction, by using a dual polarity simple threshold to enable an event driven output for neural spikes (16-sample window). The SoC additionally features a latency-encoded asynchronous output that is critical if used as part of a closed-loop system. This has been specifically developed to complement a separate on-node spike sorting co-processor to provide a real-time (low latency) output. The system has been implemented in a commercially-available 0.35μm CMOS technology occupying a silicon area of 19.1mm² (0.3mm² gross per channel), demonstrating a low power & efficient architecture which could be further optimised by aggressive technology and supply voltage scaling.

Journal article

Luan S, Williams I, De-Carvalho F, Grand L, Jackson A, Quian Quiroga R, Constandinou TGet al., 2017, Standalone headstage for neural recording with real-time spike sorting and data logging, BNA Festival of Neuroscience, Publisher: The British Neuroscience Association Ltd

Conference paper

Luan S, Liu Y, Williams I, Constandinou TGet al., 2017, An Event-Driven SoC for Neural Recording, IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 404-407

This paper presents a novel 64-channel ultra-low power/low noise neural recording System-on-Chip (SoC) featuring a highly reconfigurable Analogue Front-End (AFE) and block-selectable data-driven output. This allows a tunable bandwidth/sampling rate for extracting Local Field Potentials (LFPs)and/or Extracellular Action Potentials (EAPs). Realtime spike detection utilises a dual polarity simple threshold to enable an event driven output for neural spikes (16-sample window). The 64-channels are organised into 16 sets of 4-channel recording blocks, with each block having a dedicated 10-bit SAR ADC that is time division multiplexed among the 4 channels. Eachchannel can be individually powered down and configured for bandwidth, gain and detection threshold. The output can thus combine continuous-streaming and event-driven data packets with the system configured as SPI slave. The SoC is implemented in a commercially-available 0.35u m CMOS technology occupying a silicon area of 19.1mm^2 (0.3mm^2 gross per channel) and requiring 32uW/channel power consumption (AFE only).

Conference paper

Frehlick Z, Williams I, Constandinou TG, 2017, Improving Neural Spike Sorting Performance Using Template Enhancement, IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 524-527

This paper presents a novel method for improving the performance of template matching in neural spike sorting for similar shaped spikes, without increasing computational complexity. Mean templates for similar shaped spikes are enhanced to emphasise distinguishing features. Template optimisation is based on the variance of sample distributions. Improved spike sorting performance is demonstrated on simulated neural recordings with two and three neuron spike shapes. The method is designed for implementation on a Next Generation Neural Interface (NGNI) device at Imperial College London.

Conference paper

Williams I, Rapeaux A, Liu Y, Luan S, Constandinou TGet al., 2017, A 32-channel bidirectional neural/EMG interface with on-chip spike detection for sensorimotor feedback, IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 528-531

This paper presents a novel 32-channel bidirectional neural interface, capable of high voltage stimulation and low power, low-noise neural recording. Current-controlled biphasic pulses are output with a voltage compliance of 9.25V, user configurable amplitude (max. 315 uA) & phase duration (max. 2 ms). The low-voltage recording amplifiers consume 23 uW per channel with programmable gain between 225 - 4725. Signals are10-bit sampled at 16 kHz. Data rates are reduced by granular control of active recording channels, spike detection and event-driven communication, and repeatable multi-pulse stimulation configurations.

Conference paper

Luan S, Williams I, de Carvalho F, Jackson A, Quian Quiroga R, Constandinou TGet al., 2016, Next Generation Neural Interfaces for low-power multichannel spike sorting, FENS Forum of Neuroscience, Publisher: FENS

Conference paper

Williams I, Luan S, Jackson A, Constandinou TGet al., 2015, A scalable 32 channel neural recording and real-time FPGA based spike sorting system, IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 187-191

This demo presents a scalable a 32-channel neuralrecording platform with real-time, on-node spike sorting ca-pability. The hardware consists of: an Intan RHD2132 neuralamplifier; a low power Igloo ® nano FPGA; and an FX3 USB3.0 controller. Graphical User Interfaces for controlling thesystem, displaying real-time data, and template generation witha modified form of WaveClus are demonstrated.

Conference paper

Rapeaux A, Nikolic K, Williams I, Eftekhar A, Constandinou TGet al., 2015, Fiber size-selective stimulation using action potential filtering for a peripheral nerve interface: A simulation study, 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, Pages: 3411-3414

Functional electrical stimulation is a powerfultool for restoration of function after nerve injury. Howeverselectivity of stimulation remains an issue. This paper presentsan alternative stimulation technique to obtain fiber size-selectivestimulation of nerves using FDA-approved electrode implants.The technique was simulated for the ventral roots ofXenopus Laevis, motivated by an application in bladder control. Thetechnique relies on applying a high frequency alternatingcurrent to filter out action potentials in larger fibers, resultingin selective stimulation of the smaller fibers. Results predict thatthe technique can distinguish fibers with only a 2 µm differencein diameter (for nerves not exceeding 2 mm in diameter). Thestudy investigates the behaviour of electrically blocked nervesin detail. Model imperfections and simplifications yielded someartefacts in the results, as well as unexpected nerve behaviourwhich is tentatively explained.

Conference paper

Luan S, Williams I, Constandinou TG, Nikolic Ket al., 2014, Neuromodulation: present and emerging methods, Frontiers of Neuroengineering, Vol: 7, ISSN: 1662-6443

Neuromodulation has wide ranging potential applications in replacing impaired neural function (prosthetics), as a novel form of medical treatment (therapy), and as a tool for investigating neurons and neural function (research). Voltage and current controlled electrical neural stimulation (ENS) are methods that have already been widely applied in both neuroscience and clinical practice for neuroprosthetics. However, there are numerous alternative methods of stimulating or inhibiting neurons. This paper reviews the state-of-the-art in ENS as well as alternative neuromodulation techniques - presenting the operational concepts, technical implementation and limitations - in order to inform system design choices.

Journal article

Williams I, Constandinou TG, 2014, Computationally Efficient Modelling of Proprioceptive Signals in the Upper Limb for Prostheses: a Simulation Study, Frontiers in Neuroscience, Vol: 8, Pages: 1-13

Accurate models of proprioceptive neural patterns could one day play an important role in the creation of an intuitive proprioceptive neural prosthesis for amputees. This paper looks at combining efficient implementations of biomechanical and proprioceptor models in order to generate signals that mimic human muscular proprioceptive patterns for future experimental work in prosthesis feedback. A neuro-musculoskeletal model of the upper limb with 7 degrees of freedom and 17 muscles is presented and generates real time estimates of muscle spindle and Golgi Tendon Organ neural firing patterns. Unlike previous neuro-musculoskeletal models, muscle activation and excitation levels are unknowns in this application and an inverse dynamics tool (static optimisation) is integrated to estimate these variables. A proprioceptive prosthesis will need to be portable and this is incompatible with the computationally demanding nature of standard biomechanical and proprioceptor modelling. This paper uses and proposes a number of approximations and optimisations to make real time operation on portable hardware feasible. Finally technical obstacles to mimicking natural feedback for an intuitive proprioceptive prosthesis, as well as issues and limitations with existing models, are identified and discussed.

Journal article

Williams I, Constandinou TG, 2013, An Energy-Efficient, Dynamic Voltage Scaling Neural Stimulator for a Proprioceptive Prosthesis, IEEE Transactions on Biomedical Circuits and Systems, Vol: 7, Pages: 129-139

This paper presents an 8 channel energy-efficient neural stimulator for generating charge-balanced asymmetric pulses. Power consumption is reduced by implementing a fully integrated DC-DC converter that uses a reconfigurable switched capacitor topology to provide 4 output voltages for Dynamic Voltage Scaling (DVS). DC conversion efficiencies of up to 82% are achieved using integrated capacitances of under 1 nF and the DVS approach offers power savings of up to 50% compared to the front end of a typical current controlled neural stimulator. A novel charge balancing method is implemented which has a low level of accuracy on a single pulse and a much higher accuracy over a series of pulses. The method used is robust to process and component variation and does not require any initial or ongoing calibration. Measured results indicate that the charge imbalance is typically between 0.05% - 0.15% of charge injected for a series of pulses. Ex-vivo experiments demonstrate the viability in using this circuit for neural activation. The circuit has been implemented in a commercially-available 0.18μm HV CMOS technology and occupies a core die area of approximately 2.8mm² for an 8 channel implementation.

Journal article

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