Imperial College London

Dr James J. Davis

Faculty of EngineeringDepartment of Electrical and Electronic Engineering

Research Fellow



james.davis06 Website




906Electrical EngineeringSouth Kensington Campus





James Davis is a Research Fellow in the Department of Electrical and Electronic Engineering's Circuits and Systems group at Imperial College London.

You can find James on Google Scholar and connect with him on LinkedIn.

His research interests include:

  • Runtime monitoring of digital electronic hardware
  • Computer arithmetic
  • Neural network inference
  • Fault tolerance, reliability and lifetime extension
  • Self-adaptive systems
  • Reconfigurable computing
  • Heterogeneous and embedded systems.

James serves on the technical programme committees of the four top-tier reconfigurable computing conferences (FPGA, FCCM, FPL and FPT) and is a multi-best paper award recipient. He is a Member of the IEEE and ACM.



Li H, McInerney I, Davis J, et al., 2021, Digit Stability Inference for Iterative Methods Using Redundant Number Representation, Ieee Transactions on Computers, Vol:70, ISSN:0018-9340, Pages:1074-1080

Wang E, Davis JJ, Cheung P, et al., 2020, LUTNet: learning FPGA configurations for highly efficient neural network inference, Ieee Transactions on Computers, Vol:69, ISSN:0018-9340, Pages:1795-1808

Li H, Davis J, Wickerson J, et al., 2019, ARCHITECT: Arbitrary-precision Hardware with Digit Elision for Efficient Iterative Compute, Ieee Transactions on Very Large Scale Integration (vlsi) Systems, Vol:28, ISSN:1063-8210, Pages:516-529


Wang E, Davis J, Stavrou G-I, et al., Logic Shrinkage: Learned FPGA Netlist Sparsity for Efficient Neural Network Inference, ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, ACM

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