Imperial College London

MrJianyiCheng

Faculty of EngineeringDepartment of Electrical and Electronic Engineering

Research Postgraduate
 
 
 
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Contact

 

jianyi.cheng17

 
 
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Location

 

905Electrical EngineeringSouth Kensington Campus

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Summary

 

Summary

BIOGRAPHY

Jianyi Cheng is a Ph.D. candidate in the Circuits and Systems group, which is part of Department of Electrical and Electronic Engineering at Imperial College London.

He received his bachelor degree in BEng Electrical and Electronic Engineering at The University of Nottingham in 2017 and master's degree in MSc Analogue and Digital Integrated Circuit Design at Imperial College London in 2018. 


RESEARCH INTERESTS

His research interests include high-level synthesis (HLS), multi-threaded programs, dataflow circuit design, memory architecture and formal methods.

Publications

Conference

Cheng J, Fleming S, Chen YT, et al., EASY: efficient arbiter SYnthesis from multi-threaded code, 27th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, ACM

More Publications