Imperial College London
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ProfessorKristelFobelets

Faculty of Engineering, Department of Electrical and Electronic Engineering

Professor of Nanodevices
 
 
 
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Contact

 

+44 (0)20 7594 6236k.fobelets Website CV

 
 
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Assistant

 

Ms Susan Brace +44 (0)20 7594 6215

 
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Location

 

714Electrical EngineeringSouth Kensington Campus

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Summary

 

Publications

Citation

BibTex format

@article{Moser:2019:10.1016/j.snb.2019.04.031,
author = {Moser, N and Panteli, C and Fobelets, K and Georgiou, P},
doi = {10.1016/j.snb.2019.04.031},
journal = {Sensors and Actuators B: Chemical},
pages = {297--307},
title = {Mechanisms for enhancement of sensing performance in CMOS ISFET arrays using reactive ion etching},
url = {http://dx.doi.org/10.1016/j.snb.2019.04.031},
volume = {292},
year = {2019}
}
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RIS format (EndNote, RefMan)

TY  - JOUR
AB  - In this work, we investigate the impact of successively removing the passivation layers of ISFET sensors implemented in a standard CMOS process to improve sensing performance. Reactive ion etching is used as a post-processing technique of the CMOS chips for uniform and accurate etching. The removal of the passivation layers addresses common issues with commercial implementation of ISFET sensors, including pH sensitivity, capacitive attenuation, trapped charge, drift and noise. The process for removing the three standard layers (polyimide, Si3N4 and SiO2) is tailored to minimise the surface roughness of the sensing layer throughout an array of more than 4000 ISFET sensors. By careful calibration of the plasma recipe we perform material-wise etch steps at the top and middle of the nitride layer and top of the oxide layer. The characterisation of the ISFET array proves that the location of the trapped charge in the passivation layers is mainly at the interface of the layers. Etching to the top of the oxide layer is shown to induce an improvement of 80% in the offset range throughout the array and an increase in SNR of almost 40dB compared to the non-processed configuration. The performance enhancement demonstrates the benefit of a controlled industry-standard etch process on CMOS ISFET array system-on-chips.
AU  - Moser,N
AU  - Panteli,C
AU  - Fobelets,K
AU  - Georgiou,P
DO  - 10.1016/j.snb.2019.04.031
EP  - 307
PY  - 2019///
SN  - 0925-4005
SP  - 297
TI  - Mechanisms for enhancement of sensing performance in CMOS ISFET arrays using reactive ion etching
T2  - Sensors and Actuators B: Chemical
UR  - http://dx.doi.org/10.1016/j.snb.2019.04.031
UR  - http://hdl.handle.net/10044/1/70100
VL  - 292
ER  -
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