Imperial College London

DrKristelFobelets

Faculty of EngineeringDepartment of Electrical and Electronic Engineering

Reader in Microelectronics Engineering
 
 
 
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Contact

 

+44 (0)20 7594 6236k.fobelets Website CV

 
 
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Assistant

 

Ms Susan Brace +44 (0)20 7594 6215

 
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Location

 

714Electrical EngineeringSouth Kensington Campus

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Summary

 

Overview

I invented the Screen-Grid Field Effect Transistor. This is a FET with a novel gating structure that incorporates nanoholes. This gate geometry, not really CMOS compatible, boosts both digital as well as analogue performance and can also be exploited for biosensing. I have proposed its use as an active Coulter counter. I and my PhD student won the best invited paper award at the WOFE 2007 workshop for this work. The work was carried out in collaboration with Prof. J.E. Velazquez-Perez from the University of Salamanca in Spain. 

I used low frequency noise measurements for analyzing material problems in spintronics devices. This work was a result of a collaboration with RPI in Troy, USA and IMEC in Belgium. We received the best paper award in device reliability at the MIEL 2008 conference for using this technique. Using low frequency noise is also a powerful tool to sense small variations at the surface of the device and I have exploited this in nanowire arrays for gas sensing.

I designed the Y-branch finFET in 2010. In this FET the drain is split in two and increases the functionality of the FET. Simulations of the Y-branch finFET show an increase in speed performance and a decrease in manufacturability complexity compared to the 2 parallel connected finFETs.

My research on thermoelectric power generation uses silicon nanowire arrays attached to bulk for thermoelectric power generation. My research team achieved breakthroughs with SiGe and spin-on-doping, obtaining ~10 μW for a temperature difference of only 20°C. This is approximately 40% more than that generated by the bulk.

We used Is nanowires and investigated different methods to coat them with TiO2 for supercapacitors. The extracted energy density of a single TiO2 coated nanowire array electrode is 0.9 Wh·Kg-1 and power density is 2228 W·kg-1, placing the TiO2 coated Si NWA using a 3x Ti dip process well within the supercapacitor range on the Ragone plot.


Collaborators

Prof. J. Lusakowski, University of Warsaw, Poland, Terahertz applications, 2010

Dr. R. Loo, IMEC, Belgium, Si/SiGe growth, 2010

Dr. D. Coquillat, University of Montpellier, France, Terahertz spectroscopy, 2010

Dr. S. Roumyantsev, Ioffe Institute, Russia, low frequency noise measurements, 2006

Prof. M. Shur, Rensellaer Polytechnic Institute, Troy, USA, Solid State Devices, 2006

Prof. J. E. Velazquez-Perez, University of Salamanca, Spain, Modelling and simulation of semiconductor devices, 2001

Guest Lectures

Invited Talk - C. Li , B. Cheng, Q. Wang and K. Fobelets, “Conductance modulation of Si nanowire array”, IUMRS-ICAM International conference on advanced materials, Qingdao, China, 2013

Invited Talk - C. Li , B. Cheng, Q. Wang and K. Fobelets, “Si based nanowires for thermoelectric application”, The 2013 EMN East Meeting, Beijing, China, 2013

Invited talkChuanbo Li, Kristel Fobelets, Zahid Durrani, and Q.M. WangSi/Ge for clean energy applications, International Workshop on Group IV Nano Materials & Advanced Devices Applications, Nanjing, 2011

Research Student Supervision

Ding,PW, Development of Screen-Grid FET

Ferguson,RS, Characterisation of Silicon-Germanium Heterostuctures by Kelvin Probe Force Microscopy

Gaspari,V, Temperature effects in SiGe Modulation Doped Field Effect Transistors

Jeamsaksiri,W, Modelling and simulation of SiGe n-channel HFETs for low power applications

Li,SM, Alternative approaches to Silicon-Germanium Modulation Doped Field Effect Transistor processing

Rahman,T, Si nanowire arrays for photovoltaics

Shadrokhsikary,Y, Digital benchmarking of the SGFET

Vilches,A, SiGe HFETs micropower circuits

Xu,B, Si/SiGe nanowire arrays for thermoelectric power generation

Yuk,H-S, Fabrication of SiGe-on-insulator for strained-Si heterostructure technologies