Imperial College London
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Dr Katarzyna Szostak-Lipowicz

Faculty of Engineering, Department of Electrical and Electronic Engineering

Visiting Researcher
 
 
 
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Contact

 

k.szostak

 
 
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Location

 

Bessemer BuildingSouth Kensington Campus

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Summary

 

Publications

Citation

BibTex format

@inproceedings{Leene:2018:10.1109/ISCAS.2018.8351147,
author = {Leene, L and Maslik, M and Feng, P and Szostak, K and Mazza, F and Constandinou, TG},
doi = {10.1109/ISCAS.2018.8351147},
pages = {1--5},
publisher = {IEEE},
title = {Autonomous SoC for neural local  field potential recording in mm-scale wireless implants},
url = {http://dx.doi.org/10.1109/ISCAS.2018.8351147},
year = {2018}
}
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RIS format (EndNote, RefMan)

TY  - CPAPER
AB  - Next generation brain machine interfaces fundamentally need to improve the information transfer rate and chronic consistency when observing neural activity over a long period of time. Towards this aim, this paper presents a novel System-on-Chip (SoC) for a mm-scale wireless neural recording node that can be implanted in a distributed fashion. The proposed self-regulating architecture allows each implant to operate autonomously and adaptively load the electromagnetic field to extract a precise amount of power for full-system operation. This can allow for a large number of recording sites across multiple implants extending through cortical regions without increased control overhead in the external head-stage. By observing local field potentials (LFPs) only, chronic stability is improved and good coverage is achieved whilst reducing the spatial density of recording sites. The system features a ΔΣ based instrumentation circuit that digitises high fidelity signal features at the sensor interface thereby minimising analogue resource requirements while maintaining exceptional noise efficiency. This has been implemented in a 0.35 μm CMOS technology allowing for wafer-scale post-processing for integration of electrodes, RF coil, electronics and packaging within a 3D structure. The presented configuration will record LFPs from 8 electrodes with a 825 Hz bandwidth and an input referred noise figure of 1.77μVrms. The resulting electronics has a core area of 2.1 mm2 and a power budget of 92 μW
AU  - Leene,L
AU  - Maslik,M
AU  - Feng,P
AU  - Szostak,K
AU  - Mazza,F
AU  - Constandinou,TG
DO  - 10.1109/ISCAS.2018.8351147
EP  - 5
PB  - IEEE
PY  - 2018///
SN  - 2379-447X
SP  - 1
TI  - Autonomous SoC for neural local  field potential recording in mm-scale wireless implants
UR  - http://dx.doi.org/10.1109/ISCAS.2018.8351147
UR  - http://hdl.handle.net/10044/1/62091
ER  -
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