Summary
Peter Y. K. Cheung is Professor of Digital Systems, splitting his time between the Department of Electrical & Electronic Engineering, and Dyson School of Design Engineering. Together with Professor Wayne Luk in Department of Computing, he established one of the strongest research groups in the area of Field Programmable Gate Arrays (FPGAs) in the UK. His research in reconfigurable systems and technology include architecture, variability mitigation, reliability issues, high-level synthesis and tools, and various application area for FPGAs.
For details of research and teaching activities, please visit:
www.ee.ic.ac.uk/pcheung/
Selected Publications
Journal Articles
Wong JSJ, Cheung PYK, 2013, Timing Measurement Platform for Arbitrary Black-Box Circuits Based on Transition Probability, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol:21, ISSN:1063-8210, Pages:2307-2320
Powell A, Savvas-Bouganis C, Cheung PYK, 2013, High-level power and performance estimation of FPGA-based soft processors and its application to design space exploration, Journal of Systems Architecture, Vol:59, ISSN:1383-7621, Pages:1144-1156
Stott E, Guan Z, Levine JM, et al., 2013, Variation and Reliability in FPGAs, Ieee Design & Test, Vol:30, ISSN:2168-2356, Pages:50-59
Angelopoulou M, Bouganis C-S, Cheung PYK, 2011, Blur Identification with Assumption Validation for Sensor-based Video Reconstruction and its Implementation on FPGA, Iet Computers & Digital Techniques
Mak T, Cheung PYK, Lam KP, et al., 2011, Adaptive routing in network-on-chips using a dynamic-programming network, Ieee Transactions on Industrial Electronics, Vol:58, Pages:3701-3716
Kahoul A, Smith AM, Constantinides GA, et al., 2010, Efficient Heterogeneous Architecture Floorplan Optimization using Analytical Methods, Acm Transactions on Reconfigurable Technology and Systems, Vol:
Smith AM, Constantinides GA, Cheung PYK, 2010, An Automated Flow for Arithmetic Component Generation in Field-Programmable Gate Arrays, Acm Transactions on Reconfigurable Technology and Systems, Vol:
Smith AM, Constantinides GA, Cheung PYK, 2010, FPGA Architecture Optimization Using Geometric Programming, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol:29, ISSN:0278-0070, Pages:1163-1176
Cope B, Cheung PYK, Luk W, et al., 2010, Performance comparison of graphics processors to reconfigurable logic: a case study, IEEE Transactions on Computers, Vol:54, ISSN:0018-9340, Pages:433-448
Bouganis C, Pournara I, Cheung PYK, 2010, Exploration of Heterogeneous FPGAs for Mapping Linear Projection Designs, Ieee Transactions on Very Large Scale Integration (vlsi) Systems, Vol:18
Jamieson P, Becker T, Cheung PYK, et al., 2010, Benchmarking and evaluating reconfigurable architectures targeting the mobile domain, Acm Transactions on Design Automation of Electronic Systems (todaes), Vol:15
Mak T, Sedcole P, Cheung PYK, et al., 2010, Wave-pipelined intra-chip signaling for on-FPGA communications, Integration, the Vlsi Journal, Vol:43, Pages:188-201
Becker T, Jamieson P, Luk W, et al., 2010, Power characterisation for fine-grain reconfigurable fabrics, International Journal of Reconfigurable Computing, Vol:2010
Angelopoulou M, Bouganis CS, Cheung PYK, et al., 2009, Robust Real-Time Super-Resolution on FPGA and an Application to Video Enhancement, Acm Transactions on Reconfigurable Technology and Systems (trets), Vol:2
Fahmy SA, Cheung PYK, Luk W, 2009, High-throughput one-dimensional median and weighted median filters on FPGA, Computers & Digital Techniques, Iet, Vol:3, Pages:384-394
Wong JSJ, Sedcole P, Cheung PYK, 2009, Self-Measurement of Combinatorial Circuit Delays in FPGAs, Acm Transactions on Reconfigurable Technology and Systems (trets), Vol:2, Pages:1-22
Liu Q, Constantinides GA, Masselos K, et al., 2009, Data-reuse exploration under an on-chip memory constraint for low-power FPGA-based systems, Computers & Digital Techniques, Iet, Vol:3, Pages:235-246
Liu Q, Constantinides GA, Masselos K, et al., 2009, Combining Data Reuse With Data-Level Parallelization for FPGA-Targeted Hardware Compilation: A Geometric Programming Framework, Computer-aided Design of Integrated Circuits and Systems, Ieee Transactions On, Vol:28, Pages:305-315
Liu Y, Bouganis CS, Cheung PYK, 2009, Hardware architectures for eigenvalue computation of real symmetric matrices, Iet Proceeding on Computers & Digital Techniques, Vol:3, Pages:72-84
Bouganis CS, Park SB, Constantinides GA, et al., 2009, Synthesis and Optimization of 2D Filter Designs for Heterogeneous FPGAs, ACM Transactions on Reconfigurable Technology and Systems, Vol:1, ISSN:1936-7406
Clarke JA, Constantinides GA, Cheung PYK, 2009, Word-length selection for power minimization via non-linear optimization, Acm Transactions on Design Automation of Electronic Systems, Vol:14
Liu Q, Constantinides GA, Masselos K, et al., 2009, Compiling C-like Languages to FPGA Hardware: Some Novel Approaches Targeting Data Memory Organization, The Computer Journal, Vol: , Pages:bxp020-bxp020
Arifin S, Cheung PYK, 2008, Affective Level Video Segmentation by Utilizing the Pleasure-Arousal-Dominance Information, IEEE Transactions on Multimedia, Vol:10, ISSN:1520-9210, Pages:1325-1341
Turkington K, Constantinides GA, Masselos K, et al., 2008, Outer Loop Pipelining for Application Specific Datapaths in FPGAs, Ieee Transactions on Very Large Scale Integration (vlsi) Systems, Vol:16, Pages:1268-1280
Smith AM, Constantinides GA, Cheung PYK, 2008, Integrated Floorplanning, Module-Selection and Architecture Generation for Reconfigurable Devices, Ieee Transactions on Vlsi Systems, Vol:16, Pages:733-744
Sedcole P, Cheung PYK, 2008, Parametric Yield Modeling and Simulations of FPGA Circuits Considering Within-Die Delay Variations, ACM Transactions on Reconfigurable Technology and Systems, Vol:1, ISSN:1936-7406
Ang SS, Constantinides GA, Luk W, et al., 2008, Custom parallel caching schemes for hardware-accelerated image compression, Journal of Real-time Image Processing, Vol:3, Pages:289-302
Chapters
Liu Y, Bouganis C, Cheung PYK, 2008, Real-Time Spatiotemporal Saliency, Next generation artificial vision systems, Editor(s): Bharath, Petrou, Artech House Publishers, ISBN:9781596932241
Conference
Levine JM, Stott E, Constantinides GA, et al., 2012, Online Measurement of Timing in Circuits: for Health Monitoring and Dynamic Voltage & Frequency Scaling, 20th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), IEEE, Pages:109-116
Wong JSJ, Cheung PYK, 2011, Improved Delay Measurement Method in FPGA based on Transition Probability, 19th Annual ACM International Symposium on Field-Programmable Gate Arrays, ASSOC COMPUTING MACHINERY, Pages:163-172
Jones DH, Powell A, Bouganis C-S, et al., 2010, A Salient Region Detector for GPU Using a Cellular Automata Architecture, 17th International Conference on Neural Information Processing, SPRINGER-VERLAG BERLIN, Pages:501-508, ISSN:0302-9743
Stott EA, Wong JS, Sedcole NP, et al., 2010, Degradation in FPGAs: measurement and modelling, International symposium on field programmable gate arrays, Pages:229-238-229-238
M Angelopoulou CB, Cheung PYK, A sensor-based approach to linear blur identification for real-time video enhancement
Becker T, Luk W, Cheung PYK, 2009, Parametric Design for Reconfigurable Software-Defined Radio, 5th International Workshop on Applied Reconfigurable Computing, SPRINGER-VERLAG BERLIN, Pages:15-+, ISSN:0302-9743
Wang L, Mak T, Sedcole P, et al., 2009, Throughput Maximization for Wave-Pipelined Interconnects Using Cascaded Buffers and Transistor Sizing, IEEE International Symposium on Circuits and Systems (ISCAS 2009), IEEE, Pages:1293-1296, ISSN:0271-4302
Becker T, Jamieson P, Luk W, et al., 2009, POWER CHARACTERISATION FOR THE FABRIC IN FINE-GRAIN RECONFIGURABLE ARCHITECTURES, 5th Southern Conference on Programmable Logic, IEEE, Pages:77-+
Jamieson P, Becker T, Luk W, et al., 2009, Benchmarking Reconfigurable Architectures in the Mobile Domain, 17th Annual IEEE Symposium on Field Programmable Custom Computing Machines, IEEE COMPUTER SOC, Pages:131-+
Sedcole NP, Stott EA, Cheung PYK, 2009, Compensating for variability in FPGAs by re-mapping and re-placement, Pages:613-616-613-616
Kahoul A, Smith AM, Constantinides GA, 2009, Heterogeneous Architecture Evaluation: Analysis versus Parameter Sweep, Pages:133-144
Smith AM, Constantinides GA, Cheung PYK, 2009, Area Estimation and Optimisation of FPGA Routing Fabrics
Becker T, Jamieson P, Luk W, et al., 2008, Towards benchmarking energy efficiency of reconfigurable architectures, International Conference on Field Programmable Logic and Applications, IEEE, Pages:691-694
Mak STS, Sedcole P, Cheung PYK, et al., 2008, Interconnection lengths and delays estimation for communication links in FPGAs, The 2008 international workshop on System level interconnect prediction, ACM, Pages:1-10
Clarke JA, Constantinides GA, Cheung PYK, 2008, Glitch-Aware Output Switching Activity from Word-Level Statistics, Proc. IEEE International Symposium on Circuits and Systems, Pages:1792-1795
Angelopoulou ME, Cheung PYK, Masselos K, et al., 2008, Implementation and comparison of the 5/3 lifting 2D discrete wavelet transform computation schedules on FPGAs, 5th IEEE International Conference on Field Programmable Technology, SPRINGER, Pages:3-21, ISSN:1939-8018
Angelopoulou M, Bouganis C, Cheung PYK, et al., 2008, FPGA-based Real-time Super-Resolution on an Adaptive Image Sensor, Pages:125-136
Cope BT, Cheung PYK, Luk W, 2008, Using Reconfigurable Logic to Optimise GPU Memory Accesses, Pages:44-49
Sedcole P, Wong JS, Cheung PYK, 2008, Modelling and Compensating for Clock Skew Variability in FPGAs, International Conference on Field-Programmable Technology, IEEE, Pages:217-224
Mak T, D'Alessandro C, Sedcole P, et al., 2008, Global Interconnections in FPGAs: Modeling and Performance Analysis, ACM International Workshop on System Level Interconnect Prediction, ASSOC COMPUTING MACHINERY, Pages:51-58
Mak T, Sedcole P, Cheung PYK, et al., 2008, Wave-Pipelined Signaling for On-FPGA Communication, International Conference on Field-Programmable Technology, IEEE, Pages:9-+
Mak T, Sedcole P, Cheung PYK, et al., 2008, Interconnection Lengths and Delays Estimation for Communication Links in FPGAs, ACM International Workshop on System Level Interconnect Prediction, ASSOC COMPUTING MACHINERY, Pages:1-9
Becker T, Jamieson P, Luk W, et al., 2008, TOWARDS BENCHMARKING ENERGY EFFICIENCY OF RECONFIGURABLE ARCHITECTURES, 18th International Conference on Field Programmable and Logic Applications, IEEE, Pages:690-+, ISSN:1946-1488
Cope B, Cheung PYK, Luk W, 2008, Using reconfigurable logic to optimise GPU memory accesses, Design, Automation and Test in Europe Conference and Exhibition (DATE 08), IEEE, Pages:42-+, ISSN:1530-1591
Wong JSJ, Cheung PYK, Sedcole P, 2008, COMBATING PROCESS VARIATION ON FPGAS WITH A PRECISE AT-SPEED DELAY MEASUREMENT METHOD, 18th International Conference on Field Programmable and Logic Applications, IEEE, Pages:702-703, ISSN:1946-1488
Angelopoulou ME, Bouganis C-S, Cheung PYK, 2008, VIDEO ENHANCEMENT ON AN ADAPTIVE IMAGE SENSOR, 15th IEEE International Conference on Image Processing (ICIP 2008), IEEE, Pages:685-688, ISSN:1522-4880
Wong JSJ, Sedcole P, Cheung PYK, 2008, A Transition Probability Based Delay Measurement Method for Arbitrary Circuits on FPGAs, International Conference on Field-Programmable Technology, IEEE, Pages:105-112
Angelopoulou M, Bouganis C, Cheung PYK, et al., 2008, FPGA-based Real-time Super-Resolution on an Adaptive Image Sensor, Pages:125-136
Liu Q, Constantinides GA, Masselos K, et al., 2008, Combining Data Reuse Exploitation with Data-Level Parallelization for FPGA Targeted Hardware Compilation: A Geometric Programming Framework, Pages:179-184
Angelopoulou M, Bouganis C, Cheung PYK, 2008, Video Enhancement on an Adaptive Image Sensor, Pages:681-684
Stott E, Sedcole P, Cheung PYK, 2008, Fault tolerant methods for reliability in FPGAs, International Conference on Field Programmable Logic and Applications, IEEE, Pages:415-420
Turkington KJ, Constantinides GA, Masselos K, et al., 2008, Co-optimisation of Datapath and Memory in Outer Loop Pipelining, Pages:1-8
Patents
Cheung PYK, Sedcole NP, Wong JS, 2011, Method of Measuring Delay in An Integrated Circuit, USA, US 0095768 A1