Imperial College London

Professor Peter Y. K. Cheung

Faculty of EngineeringDyson School of Design Engineering

Head of the Dyson School of Design Engineering
 
 
 
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Contact

 

+44 (0)20 7594 6200p.cheung Website

 
 
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Assistant

 

Mrs Wiesia Hsissen +44 (0)20 7594 6261

 
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Location

 

910BElectrical EngineeringSouth Kensington Campus

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Summary

 

Publications

Publication Type
Year
to

345 results found

Sedcole P, Cheung PYK, 2006, Within-die delay variability in 90nm FPGAs and beyond, 5th IEEE International Conference on Field Programmable Technology, Publisher: IEEE, Pages: 97-+

Conference paper

Fahmy SA, Bouganis C-S, Cheung PYK, Luk Wet al., 2006, Efficient realtime FPGA implementation of the Trace Transform, 16th International Conference on Field Programmable Logic and Applications, Publisher: IEEE, Pages: 555-560, ISSN: 1946-1488

Conference paper

Rissa T, Cheung PYK, Luk W, 2006, System level design exploration of JPEG 2000 with SoftSONIC virtual hardware platform, 49th IEEE International Midwest Symposium on Circuits and Systems, Publisher: IEEE, Pages: 276-+, ISSN: 1548-3746

Conference paper

Arifin S, Cheung PYK, 2006, A novel FPGA-based implementation of time adaptive clustering for Logical Story Unit segmentation, Design, Automation and Test in Europe Conference and Exhibition (DATE 06), Publisher: IEEE, Pages: 1562-+, ISSN: 1530-1591

Conference paper

Arifin S, Cheung PYK, 2006, User attention based arousal content modeling, IEEE International Conference on Image Processing (ICIP 2006), Publisher: IEEE, Pages: 433-+, ISSN: 1522-4880

Conference paper

Liu Y, Bouganis C-S, Cheung PYK, Leong PHW, Motley SJet al., 2006, Hardware efficient architectures for eigenvalue computation, Design, Automation and Test in Europe Conference and Exhibition (DATE 06), Publisher: IEEE, Pages: 951-+, ISSN: 1530-1591

Conference paper

Todman T J, Constantinides G A, Wilton, S J E, Mencer O, Luk W, Cheung, P Y Ket al., 2006, Reconfigurable Computing: Architectures and Design Methods, System-on-Chip: Next Generation Electronics, Editors: Al-Hashimi, Publisher: IEE Press

Book chapter

Caffarena G, Constantinides G, Cheung P, Carreras C, Nieto-Taladriz Oet al., 2006, Optimal Combined Word-length Allocation and Architectural Synthesis of Digital Signal Processing Circuits, IEEE Transactions on Circuits and Systems II, Vol: 53, Pages: 339-343

Journal article

Ang S-S, Constantinides GA, Luk W, Cheung PYKet al., 2006, A Flexible Multi-Port Caching Scheme for Reconfigurable Platforms, Pages: 205-216

Conference paper

Todman, Constantinides GA, Wilton SJE, Mencer O, Luk W, Cheung PYKet al., 2006, Reconfigurable Computing: Architectures and Design Methods

Journal article

Smith AM, Constantinides GA, Cheung PYK, 2006, A Novel Heuristic and Provable Bounds for Reconfigurable Architecture Design, Pages: 521-526

Conference paper

Ang SS, Constantinides GA, Luk W, Cheung PYKet al., 2006, A flexible multi-port caching scheme for reconfigurable platforms, Proc. Applied Reconfigurable Computing

Conference paper

Sedcole P, Cheung PYK, Constantinides GA, Luk Wet al., 2006, On-Chip Communication in Run-Time Assembled Reconfigurable Systems, Pages: 168-176

Conference paper

Rissa T, Cheung PYK, Luk W, 2005, Mixed abstraction execution for the SoftSONIC virtual hardware platform, Pages: 976-979, ISSN: 1548-3746

This paper presents a systematic approach for mixed abstraction execution in the SoftSONIC virtual hardware platform. In mixed abstraction execution different levels of abstraction, for example clockless coarse granularity Transaction Level Modelling (TLM) and clocked Register Transfer Level (RTL) models can be co-simulated. When combining 10 Hz to 1 kHz-range RTL model of component under development with 100 kHz to 10 MHz-range TLM model of rest of the system, the full system simulates close to the speed of one RTL component alone. By verifying the components in full system simulation, error-prone and tedious per-component testbench generation can be avoided. Mixed abstraction execution also gives the possibility of gradual refinement and parallel development and verification of system components. These aspects can reduce the overall design time, as we show in this paper with the development of a real-time JPEG 2000 hardware encoder. © 2005 IEEE.

Conference paper

Lee DU, Luk W, Villasenor JD, Cheung PYKet al., 2005, The effects of polynomial degrees on the hierarchical segmentation method, New Algorithms, Architectures and Applications for Reconfigurable Computing, Pages: 301-313, ISBN: 9781402031274

This chapter presents the effects of polynomial degrees on the hierarchical segmentation method (HSM) for approximating functions. HSM uses a novel hierarchy of uniform segments and segments with size varying by powers of two. This scheme enables us to approximate non-linear regions of a function particularly well. The degrees of the polynomials play an important role when approximating functions with HSM: the higher the degree, the fewer segments are needed to meet the same error requirement. However, higher degree polynomials require more multipliers and adders, leading to higher circuit complexity and more delay. Hence, there is a tradeoff between table size, circuit complexity and delay. We explore these tradeoffs with four functions:, x log(x), a high order rational function and cos(πx/2). We present results for polynomials up to the fifth order for various operand sizes between 8 and 24 bits. © 2005 Springer.

Book chapter

Luk W, Cheung PYK, Shirazi N, 2005, Configurable Computing, The Electrical Engineering Handbook, Pages: 343-354, ISBN: 9780121709600

This chapter provides an overview of configurable computing and its current and future trends. Configurable computing, or reconfigurable computing, refers to the use of configurable hardware for computing purposes. The recent interest in configurable computing is mainly due to the rapid advance in technology of field-programmable gate arrays (FPGAs), devices containing a collection of programmable elements connected together by a network that may also be programmable by users. In short, FPGAs combine the flexibility of software with a performance approaching that of custom-developed hardware. FPGAs is the favored choice in implementing glue logic, experimental systems, and hardware prototypes because of advantages such as short turnaround time, user reconfigurability, and low development costs. However, there are area and time overheads for providing configurable logic, configurable storage, and configurable routing resources. This chapter adopts a broad interpretation for the term run-time reconfigurability: it includes devices that support only complete reconfiguration by the user and those that can be partially reconfigured at run time. This chapter further outlines an approach to exploit run-time reconfigurability. © 2005 Copyright © 2005 Elsevier Inc. All rights reserved.

Book chapter

Cheung RCC, Telle NJB, Luk W, Cheung PYKet al., 2005, Customizable elliptic curve cryptosystems, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, Vol: 13, Pages: 1048-1059, ISSN: 1063-8210

Journal article

Fahmy SA, Cheung PYK, Luk W, 2005, Novel FPGA-based implementation of median and weighted median filters for image processing, Proceedings of IEEE International Conference on Field Programmable Logic (FPL'05), Publisher: Institute of Electrical Engineers, Pages: 142-147

Conference paper

Bouganis C-S, Cheung, P Y K, Constantinides G Aet al., 2005, Heterogeneity Exploration for Multiple 2D Filter Designs, Pages: 263-268

Conference paper

Theerayod WT, Cheung PYK, Luk W, 2005, Hardware/software codesign, IEEE SIGNAL PROCESSING MAGAZINE, Vol: 22, Pages: 14-22, ISSN: 1053-5888

Journal article

Wiangtong T, Cheung PYK, Luk W, 2005, Hardware/software Codesign for Data-dominated DSP Applications, IEEE Signal Processing Magazine, Vol: 22, Pages: 14-22

Journal article

Fahmy SA, Cheung PYK, Luk W, 2005, Hardware acceleration of hidden Markov model decoding for person detection, Los Alamitos, Design, automation and test in europe conference and exhibition (Date 05), Munich, Germany, 7 - 11 March 2005, Publisher: IEEE Computer Soc, Pages: 8-13

Conference paper

Cheung RCC, Luk W, Cheung PYK, 2005, Reconfigurable elliptic curve cryptosystems on a chip, Los Alamitos, Design, automation and test in europe conference and exhibition (DATE 05), Munich, Germany, 7 - 11 March 2005, Publisher: IEEE Computer Soc, Pages: 24-29

Conference paper

Lee DU, Luk W, Villasenor J, Cheung PYKet al., 2005, The effects of polynomial degrees, New algorithms, architectures and applications for reconfigurable computing: 13th international conference on Field-programmable logic and applications, Lisbon, September 2003, Pages: 301-313

Conference paper

Bouganis CS, Constantinides GA, Cheung PYK, 2005, A novel 2D filter design methodology, Proceedings of IEEE international symposium on circuits and systems, Kobe, Japan, 23 - 26 May 2005, Publisher: IEEE, Pages: 532-535

Conference paper

Campregher N, Cheung PYK, Constantinides GA, Vasilko Met al., 2005, Analysis of yield loss due to random photolithographic defects in the interconnect structure of FPGAs, New York, NY, FPGA '05: proceedings of the 2005 ACM/SIGDA 13th international symposium on field-programmable gate arrays, Monterey, California, USA, 20 - 22 February 2005, Publisher: ACM Press, Pages: 138-148

Conference paper

Bouganis C-S, Constantinides GA, Cheung PYK, 2005, A Novel 2D Filter Design Methodology for Heterogeneous Devices, Pages: 13-22

Conference paper

Campregher N, Cheung PYK, Constantinides GA, Vasilko Met al., 2005, Yield modelling and yield enhancement for FPGAs using fault tolerance schemes, International Conference on Field Programmable Logic and Applications, 24 - 26 August 2005, Publisher: IEEE, Pages: 409-414

Conference paper

Hey LA, Cheung PYK, Gellman M, 2005, FPGA based router for cognitive packet networks, New York, IEEE international conference on field programmable technology, 11 - 14 December 2005, Singapore, SINGAPORE, Publisher: Ieee, Pages: 331-332

Conference paper

Cope B, Cheung PYK, Luk W, Witt Set al., 2005, Have GPUs made FPGAs redundant in the field of video processing?, New York, IEEE international conference on field programmable technology, 11 - 14 December 2005, Singapore, SINGAPORE, Publisher: Ieee, Pages: 111-118

Conference paper

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