Imperial College London

Professor Peter Y. K. Cheung

Faculty of EngineeringDyson School of Design Engineering

Head of the Dyson School of Design Engineering
 
 
 
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Contact

 

+44 (0)20 7594 6200p.cheung Website

 
 
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Assistant

 

Mrs Wiesia Hsissen +44 (0)20 7594 6261

 
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Location

 

910BElectrical EngineeringSouth Kensington Campus

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Summary

 

Publications

Publication Type
Year
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340 results found

Wong JSJ, Sedcole P, Cheung PYK, 2008, A Transition Probability Based Delay Measurement Method for Arbitrary Circuits on FPGAs, International Conference on Field-Programmable Technology, Publisher: IEEE, Pages: 105-112

Conference paper

Wong JSJ, Cheung PYK, Sedcole P, 2008, COMBATING PROCESS VARIATION ON FPGAS WITH A PRECISE AT-SPEED DELAY MEASUREMENT METHOD, International Conference on Field Programmable and Logic Applications, Publisher: IEEE, Pages: 702-703

Conference paper

Sedcole P, Wong JS, Cheung PYK, 2008, Modelling and Compensating for Clock Skew Variability in FPGAs, International Conference on Field-Programmable Technology, Publisher: IEEE, Pages: 217-224

Conference paper

Mak T, Sedcole P, Cheung PYK, Luk Wet al., 2008, Wave-Pipelined Signaling for On-FPGA Communication, International Conference on Field-Programmable Technology, Publisher: IEEE, Pages: 9-+

Conference paper

Angelopoulou ME, Bouganis C-S, Cheung PYK, 2008, VIDEO ENHANCEMENT ON AN ADAPTIVE IMAGE SENSOR, 15th IEEE International Conference on Image Processing (ICIP 2008), Publisher: IEEE, Pages: 685-688, ISSN: 1522-4880

Conference paper

Cope B, Cheung PYK, Luke W, 2008, Systematic Design Space Exploration for Customisable Multi-Processor Architectures, International Conference on Embedded Computer Systems - Architectures, Modeling and Simulation, Publisher: IEEE, Pages: 57-+

Conference paper

Cope B, Cheung PYK, Luk W, 2008, Using reconfigurable logic to optimise GPU memory accesses, Design, Automation and Test in Europe Conference and Exhibition (DATE 08), Publisher: IEEE, Pages: 42-+, ISSN: 1530-1591

Conference paper

Becker T, Jamieson P, Luk W, Cheung PYK, Rissa Tet al., 2008, TOWARDS BENCHMARKING ENERGY EFFICIENCY OF RECONFIGURABLE ARCHITECTURES, 18th International Conference on Field Programmable and Logic Applications, Publisher: IEEE, Pages: 690-+, ISSN: 1946-1488

Conference paper

Ang SS, Constantinides GA, Luk W, Cheung PYKet al., 2008, Custom parallel caching schemes for hardware-accelerated image compression, JOURNAL OF REAL-TIME IMAGE PROCESSING, Vol: 3, Pages: 289-302

In an effort to achieve lower bandwidth requirements, video compression algorithms have become increasingly complex. Consequently, the deployment of these algorithms on field programmable gate arrays (FPGAs) is becoming increasingly desirable, because of the computational parallelism on these platforms as well as the measure of flexibility afforded to designers. Typically, video data are stored in large and slow external memory arrays, but the impact of the memory access bottleneck may be reduced by buffering frequently used data in fast on-chip memories. The order of the memory accesses, resulting from many compression algorithms are dependent on the input data (Jain in Proceedings of the IEEE, pp. 349–389, 1981). These data-dependent memory accesses complicate the exploitation of data re-use, and subsequently reduce the extent to which an application may be accelerated. In this paper, we present a hybrid memory sub-system which is able to capture data re-use effectively in spite of data-dependent memory accesses. This memory sub-system is made up of a custom parallel cache and a scratchpad memory. Further, the framework is capable of exploiting 2D spatial locality, which is frequently exhibited in the access patterns of image processing applications. In a case study involving the quad-tree structured pulse code modulation (QSDPCM) application, the impact of data dependence on memory accesses is shown to be significant. In comparison with an implementation which only employs an SPM, performance improvements of up to 1.7× and 1.4× are observed through actual implementation on two modern FPGA platforms. These performance improvements are more pronounced for image sequences exhibiting greater inter-frame movements. In addition, reductions of on-chip memory resources by up to 3.2× are achievable using this framework. These results indicate that, on custom hardware platforms, there is substantial scope for improvement in the capture of data re-us

Journal article

Angelopoulou M, Bouganis C, Cheung PYK, 2008, Video Enhancement on an Adaptive Image Sensor, Pages: 681-684

Conference paper

Liu Y, Bouganis C, Cheung PYK, 2008, Real-Time Spatiotemporal Saliency, Next generation artificial vision systems, Editors: Bharath, Petrou, Publisher: Artech House Publishers, ISBN: 9781596932241

Book chapter

Angelopoulou M, Bouganis C, Cheung PYK, Constantinides GAet al., 2008, FPGA-based Real-time Super-Resolution on an Adaptive Image Sensor, Pages: 125-136

Conference paper

Turkington KJ, Constantinides GA, Masselos K, Cheung PYKet al., 2008, Co-optimisation of Datapath and Memory in Outer Loop Pipelining, Pages: 1-8

Conference paper

Liu Q, Constantinides GA, Masselos K, Cheung PYKet al., 2008, Combining Data Reuse Exploitation with Data-Level Parallelization for FPGA Targeted Hardware Compilation: A Geometric Programming Framework, Pages: 179-184

Conference paper

Stott E, Sedcole P, Cheung PYK, 2008, Fault tolerant methods for reliability in FPGAs, International Conference on Field Programmable Logic and Applications, Publisher: IEEE, Pages: 415-420

Conference paper

Fahmy SA, Bouganis C, Cheung PYK, Luk Wet al., 2007, Real-time hardware acceleration of the trace transform, Journal of Real-Time Image Processing, Vol: 2, Pages: 235-248, ISSN: 1861-8200

Journal article

Fahmy SA, Bouganis C, Cheung PYK, Luk Wet al., 2007, Real-time hardware acceleration of the trace transform, Journal of Real-Time Image Processing, Vol: 2, Pages: 235-248, ISSN: 1861-8200

Journal article

Wong JSJ, Sedcole P, Cheung PYK, 2007, Self-characterization of Combinatorial Circuit Delays in FPGAs, Pages: 17-23

Conference paper

Sedcole P, Cheung PYK, Constantinides GA, Luk Wet al., 2007, Run-Time Integration of Reconfigurable Video Processing Systems, IEEE Trans VLSI Systems, Vol: 15, Pages: 1003-1016

Journal article

Mak TST, Sedcole P, Cheung PYK, Luk Wet al., 2007, Average interconnection delay estimation for on-FPGA communication links, Electronics Letters, Vol: 43, Pages: 918-919

A new method is presented and an analytical expression is derived for average interconnection delay estimation. This method is directly applicable to predicting the average delay for high-bandwidth communication links implemented on FPGAs. The theoretical results are compared with the measured data from the actual circuits and an average error of 4.6% is reported.

Journal article

Bouganis C, Pournara I, Cheung PYK, 2007, Efficient Mapping of Dimensionality Reduction Designs onto Heterogeneous FPGAs, IEEE Symposium on Field-Programmable Custom Computing Machines, Pages: 141-150

Conference paper

Bouganis C, Pournara I, Cheung PYK, 2007, Efficient Mapping of Dimensionality Reduction Designs onto Heterogeneous FPGAs, IEEE Symposium on Field-Programmable Custom Computing Machines, Pages: 141-150

Conference paper

Wong JSJ, Sedcole P, Cheung PYK, 2007, Self-characterization of combinatorial circuit delays in FPGAs, Annual International Conference on Field Programmable Technology, Publisher: IEEE, Pages: 17-23

Conference paper

Clarke JA, Constantinides GA, Cheung PYK, 2007, On the feasibility of early routing capacitance estimation for FPGAs, 17th International Conference on Field Programmable Logic and Applications, Publisher: IEEE, Pages: 234-239, ISSN: 1946-1488

Conference paper

Mak TST, Sedcole P, Cheung PYK, Luk W, Lam KPet al., 2007, A hybrid analog-digital routing network for NoC dynamic routing, 1st International Symposium on Networks-on-Chip, Publisher: IEEE COMPUTER SOC, Pages: 173-+

Conference paper

Sedcole P, Cheung PYK, 2007, Parametric Yield in FPGAs Due to Within-die Delay Variations: A Quantitative Analysis, 15th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Publisher: ASSOC COMPUTING MACHINERY, Pages: 178-187

Conference paper

Cope B, Cheung PYK, Luk W, 2007, Bridging the gap between FPGAs and multi-processor architectures: A video processing perspective, 18th IEEE International Conference on Application-Specific Systems, Architectures and Processors, Publisher: IEEE, Pages: 308-+, ISSN: 1063-6862

Conference paper

Becker T, Luk W, Cheung PYK, 2007, Enhancing relocatability of partial bitstreams for run-time reconfiguration, 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, Publisher: IEEE COMPUTER SOC, Pages: 35-+

Conference paper

Arifin S, Cheung PYK, 2007, A novel video parsing algorithm utilizing the pleasure-arousal-dominance emotional information, IEEE International Conference on Image Processing (ICIP 2007), Publisher: IEEE, Pages: 3129-3132, ISSN: 1522-4880

Conference paper

Arifin S, Cheung PYK, 2007, A novel probabilistic approach to modeling the pleasure-arousal-dominance content of the video based on "Working memory", International Conference on Semantic Computing (ICSC 2007), Publisher: IEEE COMPUTER SOC, Pages: 147-+

Conference paper

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