Imperial College London

Professor Peter Y. K. Cheung

Faculty of EngineeringDyson School of Design Engineering

Head of the Dyson School of Design Engineering
 
 
 
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Contact

 

+44 (0)20 7594 6200p.cheung Website

 
 
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Assistant

 

Mrs Wiesia Hsissen +44 (0)20 7594 6261

 
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Location

 

910BElectrical EngineeringSouth Kensington Campus

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Summary

 

Publications

Publication Type
Year
to

340 results found

Morris GW, Constantinides GA, Cheung PYK, 2007, ROM to DSP Block Transfer for Resource Constrained Synthesis, IET Computers and Digital Techniques, Vol: 1, Pages: 17-26

Journal article

Smith AM, Constantinides GA, Cheung PYK, 2007, Fused-Arithmetic Generation for Reconfigurable Devices Using Common Subgraph Extraction, Pages: 105-112

Conference paper

Ang S-S, Constantinides GA, Luk W, Cheung PYKet al., 2007, A Hybrid Memory Sub-system for Video Coding Applications

Conference paper

Liu Y, Bouganis C-S, Cheung PYK, 2007, Efficient Mapping of a Kalman Filter into FPGA Using Tayor Expansion

Conference paper

Liu Q, Constantinides GA, Masselos K, Cheung PYKet al., 2007, Automatic On-chip Memory Minimization for Data Reuse

Conference paper

Ang S-S, Constantinides GA, Luk W, Cheung PYKet al., 2006, The Cost of Data Dependence in Motion Vector Estimation for Reconfigurable Platforms, Pages: 333-336

Conference paper

Bouganis C, Pournara I, Cheung PYK, 2006, A statistical framework for dimensionality reduction implementation in FPGAs, IEEE International Conference on Field Programmable Technology, Pages: 365-368

Conference paper

Sedcole N P, Cheung, P Y K, 2006, Within-die Delay Variability in 90nm FPGAs and Beyond, Pages: 97-104

Conference paper

Bouganis C, Pournara I, Cheung PYK, 2006, A statistical framework for dimensionality reduction implementation in FPGAs, IEEE International Conference on Field Programmable Technology, Pages: 365-368

Conference paper

Liu Y, Bouganis C-S, Cheung, P Y Ket al., 2006, A Spatiotemporal Saliency Framework, Pages: 437-440

Conference paper

Smith A M, Constantinides G A, Cheung, P Y Ket al., 2006, A Novel Heuristic and Provable Bounds for Reconfigurable Architecture Design, Pages: 521-526

Conference paper

Campregher N, Cheung, P Y K, Constantinides G A, Vasilko Met al., 2006, Reconfiguration and Fine-Grained Redundancy for Fault Tolerance in FPGAs, Pages: 455-460

Conference paper

Mak S T, Sedcole N P, Cheung, P Y K, Luk Wet al., 2006, On-FPGA Communication Architectures and Design Factors, IEEE International Conference on Field-Programmable Logic, Pages: 161-168

Conference paper

Arifin S, Cheung, P Y K, 2006, Towards Affective Level Video Applications: A novel FPGA based video Arousal Content Modeling System, IEEE International Conference on Field-Programmable Logic

Conference paper

Bouganis C, Cheung, P Y K, Li Zet al., 2006, FPGA-accelerated pre-attentive segmentation in Primary Visual Cortex, IEEE International Conference on Field-Programmable Logic

Conference paper

Fahmy S A, Bouganis C, Cheung, P Y K, Luk Wet al., 2006, Efficient Realtime FPGA Implementation of the Trace Transform, IEEE International Conference on Field-Programmable Logic, Pages: 199-204

Conference paper

Mak S T, Sedcole N P, Cheung, P Y K, Luk Wet al., 2006, On-FPGA Communication Architectures and Design Factors, IEEE International Conference on Field-Programmable Logic, Pages: 161-168

Conference paper

Sidahao N, Constantinides G A, Cheung, P Y Ket al., 2006, FPGA Implementation of Polyphase Filters Using MRM, Engineering Transactions: A Research Publication of Mahanakorn University of Tec, Vol: 1, Pages: 58-63

Journal article

Smith A M, Constantinides G A, Cheung, P Y Ket al., 2006, A Novel Heuristic and Provable Bounds for Reconfigurable Architecture Design, IEEE International Symposium on Field-Programmable Custom Computing Machines, Pages: 275-276

Conference paper

Clarke J A, Abdul Gaffar A M, Constantinides G A, Cheung, P Y Ket al., 2006, Fast word-level power models for synthesis of FPGA-based arithmetic, IEEE International Symposium on Circuits and Systems, Pages: 1299-1302

Conference paper

Clarke J A, Abdul Gaffar A M, Constantinides G A, Cheung, P Y Ket al., 2006, Fast word-level power models for synthesis of FPGA-based arithmetic, IEEE International Symposium on Circuits and Systems, Pages: 1299-1302

Conference paper

Liu Y, Bouganis C, Cheung PYK, Leong PHW, Motley SJet al., 2006, Hardware Efficient Architectures for Eigenvalue Computation, Design, Automation and Test in Europe, Pages: 953-958

Conference paper

Campregher N, Cheung, P Y K, Constantinides G A, Vasilko Met al., 2006, Yield Enhancements of Design-Specific FPGAs, Pages: 93-100

Conference paper

Liu Y, Bouganis C-S, Cheung PYK, Leong PHW, Motley SJet al., 2006, Hardware efficient architectures for eigenvalue computation, Design, Automation and Test in Europe Conference and Exhibition (DATE 06), Publisher: IEEE, Pages: 951-+, ISSN: 1530-1591

Conference paper

Arifin S, Cheung PYK, 2006, User attention based arousal content modeling, IEEE International Conference on Image Processing (ICIP 2006), Publisher: IEEE, Pages: 433-+, ISSN: 1522-4880

Conference paper

Angelopoulou M, Masselos K, Cheung P, Andreopoulos Yet al., 2006, A comparison of 2-D discrete wavelet transform computation schedules on FPGAs, 5th IEEE International Conference on Field Programmable Technology, Publisher: IEEE, Pages: 181-188

Conference paper

Rissa T, Cheung PYK, Luk W, 2006, System level design exploration of JPEG 2000 with SoftSONIC virtual hardware platform, 49th IEEE International Midwest Symposium on Circuits and Systems, Publisher: IEEE, Pages: 276-+, ISSN: 1548-3746

Conference paper

Fahmy SA, Bouganis C-S, Cheung PYK, Luk Wet al., 2006, Efficient realtime FPGA implementation of the Trace Transform, 16th International Conference on Field Programmable Logic and Applications, Publisher: IEEE, Pages: 555-560, ISSN: 1946-1488

Conference paper

Todman TJ, Constantinides GA, Wilton SJE, Mencer O, Luk W, Cheung PYKet al., 2006, Reconfigurable computing: Architectures and design methods, System-on-Chip: Next Generation Electronics, Pages: 451-494, ISBN: 9780863415524

© 2006 The Institution of Electrical Engineers and 2008 The Institution of Engineering and Technology. This chapter surveys two aspects of reconfigurable computing: architectures and design methods. The main trends in architectures are coarse-grained fabrics, heterogeneous functions and soft cores. The main trends in design methods are special purpose design methods, low power techniques and high-level transformations. We wonder what a survey of reconfigurable computing, written in 2015, will cover?.

Book chapter

Arifin S, Cheung PYK, 2006, A novel FPGA-based implementation of time adaptive clustering for Logical Story Unit segmentation, Design, Automation and Test in Europe Conference and Exhibition (DATE 06), Publisher: IEEE, Pages: 1562-+, ISSN: 1530-1591

Conference paper

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