Imperial College London

Professor Peter Y. K. Cheung

Faculty of EngineeringDyson School of Design Engineering

Head of the Dyson School of Design Engineering
 
 
 
//

Contact

 

+44 (0)20 7594 6200p.cheung Website

 
 
//

Assistant

 

Mrs Wiesia Hsissen +44 (0)20 7594 6261

 
//

Location

 

910BElectrical EngineeringSouth Kensington Campus

//

Summary

 

Publications

Publication Type
Year
to

340 results found

Campregher N, Cheung PYK, Constantinides GA, Vasilko Met al., 2005, Yield modelling and yield enhancement for FPGAs using fault tolerance schemes, International Conference on Field Programmable Logic and Applications, 24 - 26 August 2005, Publisher: IEEE, Pages: 409-414

Conference paper

Bouganis C-S, Constantinides GA, Cheung PYK, 2005, A Novel 2D Filter Design Methodology for Heterogeneous Devices, Pages: 13-22

Conference paper

Campregher N, Cheung PYK, Constantinides GA, Vasilko Met al., 2005, Analysis of yield loss due to random photolithographic defects in the interconnect structure of FPGAs, New York, NY, FPGA '05: proceedings of the 2005 ACM/SIGDA 13th international symposium on field-programmable gate arrays, Monterey, California, USA, 20 - 22 February 2005, Publisher: ACM Press, Pages: 138-148

Conference paper

Melis WJC, Turkington K, Whitton A, Luk W, Cheung PYK, Metzgen Pet al., 2005, Cell based motion estimators for reconfigurable platforms, Athens, International conference on engineering of reconfigurable systems and algorithms, 27 - 30 June 2005, Las Vegas, NV, Publisher: C S R e A Press, Pages: 218-224

Conference paper

Lee DU, Luk W, Villasenor JD, Cheung PYKet al., 2004, A Gaussian noise generator for hardware-based simulations, IEEE TRANSACTIONS ON COMPUTERS, Vol: 53, Pages: 1523-1534, ISSN: 0018-9340

Journal article

Gause J, Cheung PYK, Luk W, 2004, Reconfigurable computing for shape-adaptive video processing, IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES, Vol: 151, Pages: 313-320, ISSN: 1350-2387

Journal article

Luk W, Cheung PYK, Seng SP, 2004, Flexible Instruction Processor Systems and Methods, US 7543283

The present invention relates to the design-time and run-time environments of instruction processors implemented in reprogrammable hardware. In one aspect the present invention provides a design system for generating configuration information and associated executable code base on a customization specification, which includes application information including application source code and customization information including design constraints, for implementing an instruction processor using re-progammable hardware, the system comprising: a template generator; an analyzer; a compiler; an instantiator, and a builder. In another aspect the present invention provides a management system for managing run-time re-configuration of an instruction processor implemented using re-progrannnable hardware, comprising: a configuration library; a code library; a loader; a loader controller; a run-time monitor; an optimization determiner; and an optimization instructor.

Patent

Sim CTY, Toumazou C, Cheung PYK, 2004, Ratiometric current-mode rational DAC, ELECTRONICS LETTERS, Vol: 40, Pages: 409-410, ISSN: 0013-5194

Journal article

Cheung RCC, Brown A, Luk W, Cheung PYKet al., 2004, A scalable hardware architecture for prime number validation, 3rd International Conference on Field-Programmable Technology, Publisher: IEEE, Pages: 177-184

Conference paper

Sedcole P, Cheung PYK, Constantinides G, Luk Wet al., 2004, A structured system methodology for FPGA based system-on-a-chip design, 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, Publisher: IEEE COMPUTER SOC, Pages: 271-272

Conference paper

Ewe CT, Cheung PYK, Constantinides GA, 2004, Dual fixed-point: an efficient alternative to floating-point computation, Berlin, 14th international conference on field-programmable logic and applications, Leuven, Belgium, 30 August - 1 September 2004, Publisher: Springer-Verlag Berlin, Pages: 200-208

Conference paper

Sedcole P, Cheung PYK, Constantinides GA, Luk Wet al., 2004, A structured methodology for system-on-an-FPGA design, Berlin, 14th international conference on field-programmable logic and applications, Leuven, Belgium, 30 August - 1 September 2004, Publisher: Springer-Verlag Berlin, Pages: 1047-1051

Conference paper

Sidahao N, Constantinides GA, Cheung PYK, 2004, Multiple restricted multiplication, Berlin, 14th international conference on field-programmable logic and applications, Leuven, Belgium, 30 August - 1 September 2004, Publisher: Springer-Verlag Berlin, Pages: 374-383

Conference paper

Morris GW, Constantinides GA, Cheung PYK, 2004, Migrating functionality from ROMs to embedded multipliers, Los Alamitos, 12th annual IEEE symposium on field-programmable custom computing machines, Napa, CA, 20 - 23 April 2004, Publisher: IEEE Computer Soc, Pages: 287-288

Conference paper

Rissa T, Cheung PYK, Luk W, 2004, SoftSONIC: a customisable modular platform for video applications, Berlin, 14th international conference on field-programmable logic and applications, Leuven, Belgium, Publisher: Springer-Verlag, Pages: 54-63

Conference paper

Constantinides GA, Cheung PYK, Luk W, 2004, Synthesis and optimization of DSP algorithms, London, Publisher: Kluwer Academic Publishers, ISBN: 9781402079306

Book

Rissa T, Cheung PYK, Luk W, 2004, SoftSONIC: a customisable modular platform for video applications, Berlin, 14th international conference on field-programmable logic and applications, Leuven, Belgium, 30 August - 1 September 2004, Publisher: Springer-Verlag Berlin, Pages: 54-63

Conference paper

Morris GW, Constantinides GA, Cheung PYK, 2004, Applying word length optimisation to ROM emulation, Proceedings of IEE seminar on system on chip design, test, and techology, Pages: 1-6

Conference paper

Ewe CT, Cheung PYK, Constantinides GA, 2004, Dual Fixed Point: An Efficient Alternative to Floating Point Computation, Pages: 200-208

Conference paper

Rissa T, Luk W, Cheung PYK, 2004, Automated combination of simulation and hardware prototyping, Athens, International conference on engineering of reconfigurable systems and algorithms (ERSA 04), Las Vegas, NV, 2004, Publisher: C S R e A Press, Pages: 184-193

Conference paper

Bouganis CS, Cheung PYK, Ng J, Bharath AAet al., 2004, A steerable complex wavelet construction and its implementation on FPGA, Berlin, 14th international conference on field-programmable logic and applications, Leuven, Belgium, 30 August - 1 September 2004, Publisher: Springer-Verlag Berlin, Pages: 394-403

Conference paper

Campregher N, Cheung PYK, Vasilko M, 2004, BIST based interconnect fault location for FPGAs, Berlin, 14th international conference on field-programmable logic and applications, Leuven, Belgium, 30 August - 1 September 2004, Publisher: Springer-Verlag Berlin, Pages: 322-332

Conference paper

Hughes F, Constantinides GA, Cheung PYK, 2004, Automatic utilisation of block RAMs within handel-C, Proceedings of IEE seminar on system on chip design, test, and techology, Pages: 1-6

Conference paper

Cheung RCC, Brown A, Luk W, Cheung PYKet al., 2004, A scalable hardware architecture for prime number validation, New York, 3rd international conference on field-programmable technology DEC 06-08, 2004 Univ Queensland, Brisbane, AUSTRALIA, Publisher: IEEE, Pages: 177-184

Conference paper

Luk W, Cheung PYK, Shirazi N, 2004, Configurable computing, The electrical engineering handbook, Editors: Chen, Publisher: Elsevier Academic Press, Pages: 335-342, ISBN: 9780121709600

Book chapter

Gaffar AA, Mencer O, Luk W, Cheung PYKet al., 2004, Unifying bit-width optimisation for fixed-point and floating-point designs, Los Alamitos, 12th annual IEEE symposium on field-programmable custom computing machines, Napa, Ca, 2004, Publisher: IEEE Computer Soc, Pages: 79-88

Conference paper

Melis WJC, Cheung PYK, Luk W, 2004, Scalable structured data access by combining autonomous memory blocks, New York, 3rd international conference on field-programmable technology, University of Queensland, Brisbane, Australia, 6 - 8 December 2004, Publisher: IEEE, Pages: 457-460

Conference paper

Melis WJC, Cheung PYK, Luk W, 2004, Autonomous memory block for reconfigurable computing, New York, IEEE international symposium on circuits and systems, Vancouver, Canada, 23 - 26 May 2004, Publisher: IEEE, Pages: 581-584

Conference paper

Cheung PYK, Constantinides GA, Sousa JTD, 2004, Guest Editors’ Introduction: Field Programmable Logic and Applications, IEEE Transactions on Computers, Vol: 53, Pages: 1361-1362

Journal article

Hettiaratchi S, Cheung PYK, 2004, A novel implementation of tile-based address mapping, Los Alamitos, Design, automation and test in europe conference and exhibition (DATE 04), Paris, France, 16 - 20 February 2004, Publisher: IEEE Computer Soc, Pages: 306-311

Conference paper

This data is extracted from the Web of Science and reproduced under a licence from Thomson Reuters. You may not copy or re-distribute this data in whole or in part without the written consent of the Science business of Thomson Reuters.

Request URL: http://wlsprd.imperial.ac.uk:80/respub/WEB-INF/jsp/search-html.jsp Request URI: /respub/WEB-INF/jsp/search-html.jsp Query String: id=00001081&limit=30&person=true&page=7&respub-action=search.html