Imperial College London

Professor Peter Y. K. Cheung

Faculty of EngineeringDyson School of Design Engineering

Head of the Dyson School of Design Engineering



+44 (0)20 7594 6200p.cheung Website




Mrs Wiesia Hsissen +44 (0)20 7594 6261




910BElectrical EngineeringSouth Kensington Campus






BibTex format

author = {Wang, E and Davis, J and Cheung, P and Constantinides, G},
doi = {10.1109/FCCM.2019.00014},
pages = {26--34},
publisher = {IEEE},
title = {LUTNet: Rethinking Inference in FPGA Soft Logic},
url = {},
year = {2019}

RIS format (EndNote, RefMan)

AB - Research has shown that deep neural networks contain significant redundancy, and that high classification accuracies can be achieved even when weights and activations are quantised down to binary values. Network binarisation on FPGAs greatly increases area efficiency by replacing resource-hungry multipliers with lightweight XNOR gates. However, an FPGA's fundamental building block, the K-LUT, is capable of implementing far more than an XNOR: it can perform any K-input Boolean operation. Inspired by this observation, we propose LUTNet, an end-to-end hardware-software framework for the construction of area-efficient FPGA-based neural network accelerators using the native LUTs as inference operators. We demonstrate that the exploitation of LUT flexibility allows for far heavier pruning than possible in prior works, resulting in significant area savings while achieving comparable accuracy. Against the state-of-the-art binarised neural network implementation, we achieve twice the area efficiency for several standard network models when inferencing popular datasets. We also demonstrate that even greater energy efficiency improvements are obtainable.
AU - Wang,E
AU - Davis,J
AU - Cheung,P
AU - Constantinides,G
DO - 10.1109/FCCM.2019.00014
EP - 34
PY - 2019///
SP - 26
TI - LUTNet: Rethinking Inference in FPGA Soft Logic
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UR -
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ER -