Imperial College London

Professor Peter Y. K. Cheung

Faculty of EngineeringDyson School of Design Engineering

Head of the Dyson School of Design Engineering
 
 
 
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Contact

 

+44 (0)20 7594 6200p.cheung Website

 
 
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Assistant

 

Mrs Wiesia Hsissen +44 (0)20 7594 6261

 
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Location

 

910BElectrical EngineeringSouth Kensington Campus

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Summary

 

Publications

Citation

BibTex format

@inproceedings{Wang:2019:10.1109/FCCM.2019.00014,
author = {Wang, E and Davis, J and Cheung, P and Constantinides, G},
doi = {10.1109/FCCM.2019.00014},
pages = {26--34},
publisher = {IEEE},
title = {LUTNet: Rethinking Inference in FPGA Soft Logic},
url = {http://dx.doi.org/10.1109/FCCM.2019.00014},
year = {2019}
}

RIS format (EndNote, RefMan)

TY  - CPAPER
AB - Research has shown that deep neural networks contain significant redundancy, and that high classification accuracies can be achieved even when weights and activations are quantised down to binary values. Network binarisation on FPGAs greatly increases area efficiency by replacing resource-hungry multipliers with lightweight XNOR gates. However, an FPGA's fundamental building block, the K-LUT, is capable of implementing far more than an XNOR: it can perform any K-input Boolean operation. Inspired by this observation, we propose LUTNet, an end-to-end hardware-software framework for the construction of area-efficient FPGA-based neural network accelerators using the native LUTs as inference operators. We demonstrate that the exploitation of LUT flexibility allows for far heavier pruning than possible in prior works, resulting in significant area savings while achieving comparable accuracy. Against the state-of-the-art binarised neural network implementation, we achieve twice the area efficiency for several standard network models when inferencing popular datasets. We also demonstrate that even greater energy efficiency improvements are obtainable.
AU - Wang,E
AU - Davis,J
AU - Cheung,P
AU - Constantinides,G
DO - 10.1109/FCCM.2019.00014
EP - 34
PB - IEEE
PY - 2019///
SP - 26
TI - LUTNet: Rethinking Inference in FPGA Soft Logic
UR - http://dx.doi.org/10.1109/FCCM.2019.00014
UR - https://arxiv.org/abs/1904.00938
UR - https://ieeexplore.ieee.org/document/8735521
UR - http://hdl.handle.net/10044/1/68384
ER -