Imperial College London

Professor Peter Y. K. Cheung

Faculty of EngineeringDyson School of Design Engineering

Head of the Dyson School of Design Engineering
 
 
 
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Contact

 

+44 (0)20 7594 6200p.cheung Website

 
 
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Assistant

 

Mrs Wiesia Hsissen +44 (0)20 7594 6261

 
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Location

 

910BElectrical EngineeringSouth Kensington Campus

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Summary

 

Publications

Citation

BibTex format

@inproceedings{Li:2018:10.1109/FPT.2018.00044,
author = {Li, Q and Fleming, ST and Thomas, DB and Cheung, PYK},
doi = {10.1109/FPT.2018.00044},
pages = {245--248},
publisher = {IEEE COMPUTER SOC},
title = {Accelerating Top-k ListNet Training for Ranking Using FPGA},
url = {http://dx.doi.org/10.1109/FPT.2018.00044},
year = {2018}
}

RIS format (EndNote, RefMan)

TY  - CPAPER
AU - Li,Q
AU - Fleming,ST
AU - Thomas,DB
AU - Cheung,PYK
DO - 10.1109/FPT.2018.00044
EP - 248
PB - IEEE COMPUTER SOC
PY - 2018///
SP - 245
TI - Accelerating Top-k ListNet Training for Ranking Using FPGA
UR - http://dx.doi.org/10.1109/FPT.2018.00044
UR - http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000491322000036&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=1ba7043ffcc86c417c072aa74d649202
ER -