Imperial College London

Professor Peter Y. K. Cheung

Faculty of EngineeringDyson School of Design Engineering

Head of the Dyson School of Design Engineering
 
 
 
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Contact

 

+44 (0)20 7594 6200p.cheung Website

 
 
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Assistant

 

Mrs Wiesia Hsissen +44 (0)20 7594 6261

 
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Location

 

910BElectrical EngineeringSouth Kensington Campus

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Summary

 

Publications

Citation

BibTex format

@inproceedings{Clarke:2007:10.1109/FPL.2007.4380653,
author = {Clarke, JA and Constantinides, GA and Cheung, PYK},
doi = {10.1109/FPL.2007.4380653},
pages = {234--239},
publisher = {IEEE},
title = {On the feasibility of early routing capacitance estimation for FPGAs},
url = {http://dx.doi.org/10.1109/FPL.2007.4380653},
year = {2007}
}

RIS format (EndNote, RefMan)

TY  - CPAPER
AU - Clarke,JA
AU - Constantinides,GA
AU - Cheung,PYK
DO - 10.1109/FPL.2007.4380653
EP - 239
PB - IEEE
PY - 2007///
SN - 1946-1488
SP - 234
TI - On the feasibility of early routing capacitance estimation for FPGAs
UR - http://dx.doi.org/10.1109/FPL.2007.4380653
UR - http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000252360200037&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=1ba7043ffcc86c417c072aa74d649202
ER -