Imperial College London

Professor Peter Y. K. Cheung

Faculty of EngineeringDyson School of Design Engineering

Head of the Dyson School of Design Engineering
 
 
 
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Contact

 

+44 (0)20 7594 6200p.cheung Website

 
 
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Assistant

 

Mrs Wiesia Hsissen +44 (0)20 7594 6261

 
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Location

 

910BElectrical EngineeringSouth Kensington Campus

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Summary

 

Publications

Citation

BibTex format

@article{Mak:2007:10.1049/el:20071342,
author = {Mak, TST and Sedcole, P and Cheung, PYK and Luk, W},
doi = {10.1049/el:20071342},
journal = {Electronics Letters},
pages = {918--919},
title = {Average interconnection delay estimation for on-FPGA communication links},
url = {http://dx.doi.org/10.1049/el:20071342},
volume = {43},
year = {2007}
}

RIS format (EndNote, RefMan)

TY  - JOUR
AB - A new method is presented and an analytical expression is derived for average interconnection delay estimation. This method is directly applicable to predicting the average delay for high-bandwidth communication links implemented on FPGAs. The theoretical results are compared with the measured data from the actual circuits and an average error of 4.6% is reported.
AU - Mak,TST
AU - Sedcole,P
AU - Cheung,PYK
AU - Luk,W
DO - 10.1049/el:20071342
EP - 919
PY - 2007///
SP - 918
TI - Average interconnection delay estimation for on-FPGA communication links
T2 - Electronics Letters
UR - http://dx.doi.org/10.1049/el:20071342
VL - 43
ER -