Imperial College London

Professor Peter Y. K. Cheung

Faculty of EngineeringDyson School of Design Engineering

Head of the Dyson School of Design Engineering
 
 
 
//

Contact

 

+44 (0)20 7594 6200p.cheung Website

 
 
//

Assistant

 

Mrs Wiesia Hsissen +44 (0)20 7594 6261

 
//

Location

 

910BElectrical EngineeringSouth Kensington Campus

//

Summary

 

Publications

Citation

BibTex format

@article{Smith:2010:10.1109/TCAD.2010.2049046,
author = {Smith, AM and Constantinides, GA and Cheung, PYK},
doi = {10.1109/TCAD.2010.2049046},
journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
pages = {1163--1176},
title = {FPGA Architecture Optimization Using Geometric Programming},
url = {http://dx.doi.org/10.1109/TCAD.2010.2049046},
volume = {29},
year = {2010}
}

RIS format (EndNote, RefMan)

TY  - JOUR
AB - This paper is concerned with the application of geometric programming to the design of homogeneous field programmable gate array (FPGA) architectures. The paper builds on an increasing body of work concerned with modeling reconfigurable architectures, and presents a full area and delay model of an FPGA. We use a geometric programming framework to show how transistor sizing and high-level architecture parameter selection can now be solved as a concurrent optimization problem. We validate the model through the use of simulation program with integrated circuit emphasis (SPICE) models and the versatile place and route (VPR) FPGA architecture simulation tool. Not only does the optimization framework allow architectures to be optimized orders of magnitude faster than previous work, but the combined optimization can lead to different architectural conclusions compared to conventional methods by exploring the coupling between the two sets of optimization variables. Specifically, we show that as delay takes more significance in the objective of the optimization, there should be more lookup tables in a logic block, whereas conventional techniques suggest that there should be fewer lookup tables in an FPGA logic block.
AU - Smith,AM
AU - Constantinides,GA
AU - Cheung,PYK
DO - 10.1109/TCAD.2010.2049046
EP - 1176
PY - 2010///
SN - 0278-0070
SP - 1163
TI - FPGA Architecture Optimization Using Geometric Programming
T2 - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
UR - http://dx.doi.org/10.1109/TCAD.2010.2049046
UR - http://hdl.handle.net/10044/1/15304
VL - 29
ER -