Imperial College London

Professor Peter Y. K. Cheung

Faculty of EngineeringDyson School of Design Engineering

Head of the Dyson School of Design Engineering
 
 
 
//

Contact

 

+44 (0)20 7594 6200p.cheung Website

 
 
//

Assistant

 

Mrs Wiesia Hsissen +44 (0)20 7594 6261

 
//

Location

 

910BElectrical EngineeringSouth Kensington Campus

//

Summary

 

Publications

Citation

BibTex format

@article{Cope:2010:10.1109/TC.2009.179,
author = {Cope, B and Cheung, PYK and Luk, W and Howes, L and Cope, B and Cheung, PYK and Luk, W and Howes, L},
doi = {10.1109/TC.2009.179},
journal = {IEEE Transactions on Computers},
pages = {433--448},
title = {Performance comparison of graphics processors to reconfigurable logic: a case study},
url = {http://dx.doi.org/10.1109/TC.2009.179},
volume = {54},
year = {2010}
}

RIS format (EndNote, RefMan)

TY  - JOUR
AB - A systematic approach to the comparison of the graphics processor (GPU) and reconfigurable logic is defined in terms of three throughput drivers. The approach is applied to five case study algorithms, characterized by their arithmetic complexity, memory access requirements, and data dependence, and two target devices: the nVidia GeForce 7900 GTX GPU and a Xilinx Virtex-4 field programmable gate array (FPGA). Two orders of magnitude speedup, over a general-purpose processor, is observed for each device for arithmetic intensive algorithms. An FPGA is superior, over a GPU, for algorithms requiring large numbers of regular memory accesses, while the GPU is superior for algorithms with variable data reuse. In the presence of data dependence, the implementation of a customized data path in an FPGA exceeds GPU performance by up to eight times. The trends of the analysis to newer and future technologies are analyzed.
AU - Cope,B
AU - Cheung,PYK
AU - Luk,W
AU - Howes,L
AU - Cope,B
AU - Cheung,PYK
AU - Luk,W
AU - Howes,L
DO - 10.1109/TC.2009.179
EP - 448
PY - 2010///
SN - 0018-9340
SP - 433
TI - Performance comparison of graphics processors to reconfigurable logic: a case study
T2 - IEEE Transactions on Computers
UR - http://dx.doi.org/10.1109/TC.2009.179
VL - 54
ER -