Imperial College London

Professor Peter Y. K. Cheung

Faculty of EngineeringDyson School of Design Engineering

Head of the Dyson School of Design Engineering



+44 (0)20 7594 6200p.cheung Website




Mrs Wiesia Hsissen +44 (0)20 7594 6261




910BElectrical EngineeringSouth Kensington Campus






BibTex format

author = {Becker, T and Jamieson, P and Luk, W and Cheung, PYK and Rissa, T},
doi = {2010/787405},
journal = {International Journal of Reconfigurable Computing},
title = {Power characterisation for fine-grain reconfigurable fabrics},
url = {},
volume = {2010},
year = {2010}

RIS format (EndNote, RefMan)

AB - This paper proposes a benchmarking methodology for characterising the power consumption of the fine-grain fabric in reconfigurable architectures. This methodology is part of the GroundHog 2009 power benchmarking suite. It covers active and inactive power as well as advanced low-power modes. A method based on random number generators is adopted for comparing activity modes. We illustrate our approach using five field-programmable gate arrays (FPGAs) that span a range of process technologies: Xilinx Virtex-II Pro, Spartan-3E, Spartan-3AN, Virtex-5, and Silicon Blue iCE65. We find that, despite improvements through process technology and low-power modes, current devices need further improvements to be sufficiently power efficient for mobile applications. The Silicon Blue device demonstrates that performance can be traded off to achieve lower leakage.
AU - Becker,T
AU - Jamieson,P
AU - Luk,W
AU - Cheung,PYK
AU - Rissa,T
DO - 2010/787405
PY - 2010///
TI - Power characterisation for fine-grain reconfigurable fabrics
T2 - International Journal of Reconfigurable Computing
UR -
VL - 2010
ER -