Imperial College London

Professor Peter Y. K. Cheung

Faculty of EngineeringDyson School of Design Engineering

Head of the Dyson School of Design Engineering



+44 (0)20 7594 6200p.cheung Website




Mrs Wiesia Hsissen +44 (0)20 7594 6261




910BElectrical EngineeringSouth Kensington Campus






BibTex format

author = {Mak, T and Sedcole, P and Cheung, PYK and Luk, W},
doi = {10.1016/j.vlsi.2010.01.002},
journal = {Integration, the VLSI Journal},
pages = {188--201},
title = {Wave-pipelined intra-chip signaling for on-FPGA communications},
url = {},
volume = {43},
year = {2010}

RIS format (EndNote, RefMan)

AB - On-FPGA communication is becoming more problematic as the long interconnection performance is deteriorating in technology scaling. In this paper, we address this issue by proposing a novel wave-pipelined signaling scheme to achieve substantial throughput improvement in FPGAs. A new analytical model capturing the electrical characteristics in FPGA interconnects is presented. Based on the model, throughput and power consumption of a wave-pipelined link have been derived analytically and compared to the conventional synchronous links. Two circuit designs are proposed to realize wave-pipelined link using FPGA fabrics. The proposed approaches are also compared with conventional synchronous and asynchronous pipelining techniques. It is shown that the wave-pipelined approach can achieve up to 5.7 times improvement in throughput and 13% improvement in power consumption versus conventional delay-based on-chip communication schemes. Also, trade-offs between power, throughput and area consumption between the proposed and conventional designs are studied. The wave-pipelining approach provides a new alternative for on-FPGA communications and can potentially become a promising solution to mitigate the future interconnect scaling challenge.
AU - Mak,T
AU - Sedcole,P
AU - Cheung,PYK
AU - Luk,W
DO - 10.1016/j.vlsi.2010.01.002
EP - 201
PY - 2010///
SP - 188
TI - Wave-pipelined intra-chip signaling for on-FPGA communications
T2 - Integration, the VLSI Journal
UR -
VL - 43
ER -