Imperial College London

Professor Peter Y. K. Cheung

Faculty of EngineeringDyson School of Design Engineering

Head of the Dyson School of Design Engineering
 
 
 
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Contact

 

+44 (0)20 7594 6200p.cheung Website

 
 
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Assistant

 

Mrs Wiesia Hsissen +44 (0)20 7594 6261

 
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Location

 

910BElectrical EngineeringSouth Kensington Campus

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Summary

 

Publications

Citation

BibTex format

@misc{Cheung:2011,
author = {Cheung, PYK and Sedcole, NP and Wong, JS},
title = {Method of Measuring Delay in An Integrated Circuit},
type = {Patent},
year = {2011}
}

RIS format (EndNote, RefMan)

TY  - PAT
AB - A method of measuring signal delay in a integrated circuit comprising applying a common clock signal at a circuit input and output, applying a test signal at the circuit input, detecting a corresponding output signal at the circuit output and detecting whether the test signal and output signal occur in a common part of the clock signal.
AU - Cheung,PYK
AU - Sedcole,NP
AU - Wong,JS
PY - 2011///
TI - Method of Measuring Delay in An Integrated Circuit
ER -