Imperial College London

Professor Peter Y. K. Cheung

Faculty of EngineeringDyson School of Design Engineering

Head of the Dyson School of Design Engineering
 
 
 
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Contact

 

+44 (0)20 7594 6200p.cheung Website

 
 
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Assistant

 

Mrs Wiesia Hsissen +44 (0)20 7594 6261

 
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Location

 

910BElectrical EngineeringSouth Kensington Campus

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Summary

 

Publications

Citation

BibTex format

@article{Guan:2014:10.1587/elex.10.20130912,
author = {Guan, Z and Wong, JSJ and Chaudhuri, S and Constantinides, G and Cheung, PYK},
doi = {10.1587/elex.10.20130912},
journal = {IEICE ELECTRONICS EXPRESS},
title = {Classification on variation maps: a new placement strategy to alleviate process variation on FPGA},
url = {http://dx.doi.org/10.1587/elex.10.20130912},
volume = {11},
year = {2014}
}

RIS format (EndNote, RefMan)

TY  - JOUR
AU - Guan,Z
AU - Wong,JSJ
AU - Chaudhuri,S
AU - Constantinides,G
AU - Cheung,PYK
DO - 10.1587/elex.10.20130912
PY - 2014///
SN - 1349-2543
TI - Classification on variation maps: a new placement strategy to alleviate process variation on FPGA
T2 - IEICE ELECTRONICS EXPRESS
UR - http://dx.doi.org/10.1587/elex.10.20130912
UR - http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000333894200001&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=1ba7043ffcc86c417c072aa74d649202
VL - 11
ER -