Imperial College London

Professor Peter Y. K. Cheung

Faculty of EngineeringDyson School of Design Engineering

Head of the Dyson School of Design Engineering
 
 
 
//

Contact

 

+44 (0)20 7594 6200p.cheung Website

 
 
//

Assistant

 

Mrs Wiesia Hsissen +44 (0)20 7594 6261

 
//

Location

 

910BElectrical EngineeringSouth Kensington Campus

//

Summary

 

Publications

Citation

BibTex format

@inproceedings{Liu:2008,
author = {Liu, Q and Constantinides, GA and Masselos, K and Cheung, PYK},
pages = {179--184},
title = {Combining Data Reuse Exploitation with Data-Level Parallelization for FPGA Targeted Hardware Compilation: A Geometric Programming Framework},
year = {2008}
}

RIS format (EndNote, RefMan)

TY  - CPAPER
AU - Liu,Q
AU - Constantinides,GA
AU - Masselos,K
AU - Cheung,PYK
EP - 184
PY - 2008///
SP - 179
TI - Combining Data Reuse Exploitation with Data-Level Parallelization for FPGA Targeted Hardware Compilation: A Geometric Programming Framework
ER -