Imperial College London

Professor Peter Y. K. Cheung

Faculty of EngineeringDyson School of Design Engineering

Head of the Dyson School of Design Engineering



+44 (0)20 7594 6200p.cheung Website




Mrs Wiesia Hsissen +44 (0)20 7594 6261




910BElectrical EngineeringSouth Kensington Campus






BibTex format

author = {Davis, JJ and Cheung, PYK},
doi = {10.1109/FPT.2013.6718389},
pages = {366--369},
publisher = {IEEE},
title = {Datapath Fault Tolerance for Parallel Accelerators},
url = {},
year = {2014}

RIS format (EndNote, RefMan)

AB - While we reap the benefits of process scaling in terms of transistor density and switching speed, consideration must be given to the negative effects it causes: increased variation, degradation and fault susceptibility. Above device level, such phenomena and the faults they induce can lead to reduced yield, decreased system reliability and, in extreme cases, total failure after a period of successful operation. Although error detection and correction are almost always considered for highly sensitive and susceptible applications such as those in space, for other, more general-purpose applications they are often overlooked. In this paper, we present a parallel matrix multiplication accelerator running in hardware on the Xilinx Zynq system-on-chip platform, along with 'bolt-on' logic for detecting, locating and avoiding faults within its datapath. Designs of various sizes are compared with respect to resource overhead and performance impact. Our largest-implemented fault-tolerant accelerator was found to consume 17.3% more area, run at a 3.95% lower frequency and incur an 18.8% execution time penalty over its equivalent fault-susceptible design during fault-free operation.
AU - Davis,JJ
AU - Cheung,PYK
DO - 10.1109/FPT.2013.6718389
EP - 369
PY - 2014///
SP - 366
TI - Datapath Fault Tolerance for Parallel Accelerators
UR -
UR -
UR -
ER -