Imperial College London

Professor Peter Y. K. Cheung

Faculty of EngineeringDyson School of Design Engineering

Head of the Dyson School of Design Engineering
 
 
 
//

Contact

 

+44 (0)20 7594 6200p.cheung Website

 
 
//

Assistant

 

Mrs Wiesia Hsissen +44 (0)20 7594 6261

 
//

Location

 

910BElectrical EngineeringSouth Kensington Campus

//

Summary

 

Publications

Citation

BibTex format

@inproceedings{Davis:2014:10.1109/FCCM.2014.36,
author = {Davis, J and Cheung, PYK},
doi = {10.1109/FCCM.2014.36},
pages = {103--103},
publisher = {IEEE},
title = {Reducing Overheads for Fault-tolerant Datapaths with Dynamic Partial Reconfiguration},
url = {http://dx.doi.org/10.1109/FCCM.2014.36},
year = {2014}
}

RIS format (EndNote, RefMan)

TY  - CPAPER
AB - As process scaling and transistor count inflation continue, silicon chips are becoming increasingly susceptible to faults. Although FPGAs are particularly vulnerable to these effects, their runtime reconfigurability offers unique opportunities for fault tolerance. This work presents an application combining algorithmic-level error detection with dynamic partial reconfiguration (DPR) to allow faults manifested within its datapath at runtime to be circumvented at low cost.
AU - Davis,J
AU - Cheung,PYK
DO - 10.1109/FCCM.2014.36
EP - 103
PB - IEEE
PY - 2014///
SP - 103
TI - Reducing Overheads for Fault-tolerant Datapaths with Dynamic Partial Reconfiguration
UR - http://dx.doi.org/10.1109/FCCM.2014.36
UR - http://ieeexplore.ieee.org/document/6861598/
UR - http://hdl.handle.net/10044/1/23355
ER -