Imperial College London

Professor Peter Y. K. Cheung

Faculty of EngineeringDyson School of Design Engineering

Head of the Dyson School of Design Engineering



+44 (0)20 7594 6200p.cheung Website




Mrs Wiesia Hsissen +44 (0)20 7594 6261




910BElectrical EngineeringSouth Kensington Campus






BibTex format

author = {Davis, J and Levine, J and Stott, E and Hung, E and Cheung, P and Constantinides, GA},
doi = {10.23919/FPL.2017.8056842},
publisher = {IEEE},
title = {STRIPE: Signal Selection for Runtime Power Estimation},
url = {},
year = {2017}

RIS format (EndNote, RefMan)

AB - Knowledge of power consumption at a subsystem level can facilitate adaptive energy-saving techniques such as power gating, runtime task mapping and dynamic voltage and/or frequency scaling. While we have the ability to attribute power to an arbitrary hardware system's modules in real time, the selection of the particular signals to monitor for the purpose of power estimation within any given module has yet to be treated as a primary concern. In this paper, we show how the automatic analysis of circuit structure and behaviour inferred through vectored simulation can be used to produce high-quality rankings of signals' importance, with the resulting selections able to achieve lower power estimation error than those of prior work coupled with decreases in area, power and modelling complexity. In particular, by monitoring just eight signals per module (~0.3% of the total) across the 15 we examined, we demonstrate how to achieve runtime module-level estimation errors 1.5--6.9x lower than when reliant on the signal selections made in accordance with a more straightforward, previously published metric.
AU - Davis,J
AU - Levine,J
AU - Stott,E
AU - Hung,E
AU - Cheung,P
AU - Constantinides,GA
DO - 10.23919/FPL.2017.8056842
PY - 2017///
TI - STRIPE: Signal Selection for Runtime Power Estimation
UR -
UR -
UR -
UR -
ER -