Imperial College London

Professor Peter Y. K. Cheung

Faculty of EngineeringDyson School of Design Engineering

Head of the Dyson School of Design Engineering



+44 (0)20 7594 6200p.cheung Website




Mrs Wiesia Hsissen +44 (0)20 7594 6261




910BElectrical EngineeringSouth Kensington Campus






BibTex format

author = {Davis, JJ and Levine, JM and Stott, EA and Hung, E and Cheung, PYK and Constantinides, GA},
doi = {10.1109/MDAT.2017.2750909},
journal = {IEEE Design and Test},
pages = {36--45},
title = {KOCL: Power Self-awareness for Arbitrary FPGA-SoC-accelerated OpenCL Applications},
url = {},
volume = {34},
year = {2017}

RIS format (EndNote, RefMan)

AB - Given the need for developers to rapidly produce complex, high-performance and energy-efficient hardware systems, methods facilitating their intelligent runtime management are of ever-increasing importance. For energy optimization, such control decisions require knowledge of power usage at subsystem granularity. This information must be made accessible to developers now accustomed to creating systems from high-level descriptions, such as those written in OpenCL. To address these challenges, we introduce KOCL, a tool allowing OpenCL developers targeting FPGA-SoC devices to query live kernel-level power consumption using function calls embedded in their host code. KOCL is open-source, available online at To maximize accessibility, its use necessitates zero exposure to hardware.
AU - Davis,JJ
AU - Levine,JM
AU - Stott,EA
AU - Hung,E
AU - Cheung,PYK
AU - Constantinides,GA
DO - 10.1109/MDAT.2017.2750909
EP - 45
PY - 2017///
SN - 2168-2356
SP - 36
TI - KOCL: Power Self-awareness for Arbitrary FPGA-SoC-accelerated OpenCL Applications
T2 - IEEE Design and Test
UR -
UR -
UR -
VL - 34
ER -