Imperial College London

Professor Peter Y. K. Cheung

Faculty of EngineeringDyson School of Design Engineering

Head of the Dyson School of Design Engineering
 
 
 
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Contact

 

+44 (0)20 7594 6200p.cheung Website

 
 
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Assistant

 

Mrs Wiesia Hsissen +44 (0)20 7594 6261

 
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Location

 

910BElectrical EngineeringSouth Kensington Campus

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Summary

 

Publications

Citation

BibTex format

@article{Davis:2018:10.1145/3129789,
author = {Davis, JJ and Hung, E and Levine, JM and Stott, EA and Cheung, PYK and Constantinides, GA},
doi = {10.1145/3129789},
journal = {ACM Transactions on Reconfigurable Technology and Systems},
pages = {2:1--2:22},
title = {KAPow: High-accuracy, Low-overhead Online Per-module Power Estimation for FPGA Designs},
url = {http://dx.doi.org/10.1145/3129789},
volume = {11},
year = {2018}
}

RIS format (EndNote, RefMan)

TY  - JOUR
AB - In an FPGA system-on-chip design, it is often insufficient to merely assess the power consumption of the entire circuit by compile-time estimation or runtime power measurement. Instead, to make better decisions, one must understand the power consumed by each module in the system. In this work, we combine measurements of register-level switching activity and system-level power to build an adaptive online model that produces live breakdowns of power consumption within the design. Online model refinement avoids time-consuming characterisation while also allowing the model to track long-term operating condition changes. Central to our method is an automated flow that selects signals predicted to be indicative of high power consumption, instrumenting them for monitoring. We named this technique KAPow, for 'K'ounting Activity for Power estimation, which we show to be accurate and to have low overheads across a range of representative benchmarks. We also propose a strategy allowing for the identification and subsequent elimination of counters found to be of low significance at runtime, reducing algorithmic complexity without sacrificing significant accuracy. Finally, we demonstrate an application example in which a module-level power breakdown can be used to determine an efficient mapping of tasks to modules and reduce system-wide power consumption by up to 7%.
AU - Davis,JJ
AU - Hung,E
AU - Levine,JM
AU - Stott,EA
AU - Cheung,PYK
AU - Constantinides,GA
DO - 10.1145/3129789
EP - 1
PY - 2018///
SN - 1936-7406
SP - 2
TI - KAPow: High-accuracy, Low-overhead Online Per-module Power Estimation for FPGA Designs
T2 - ACM Transactions on Reconfigurable Technology and Systems
UR - http://dx.doi.org/10.1145/3129789
UR - http://cas.ee.ic.ac.uk/people/gac1/pubs/JamesTRETS17.pdf
UR - https://dl.acm.org/citation.cfm?id=3129789
UR - http://hdl.handle.net/10044/1/50304
VL - 11
ER -