Imperial College London

Professor Peter Y. K. Cheung

Faculty of EngineeringDyson School of Design Engineering

Head of the Dyson School of Design Engineering
 
 
 
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Contact

 

+44 (0)20 7594 6200p.cheung Website

 
 
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Assistant

 

Mrs Wiesia Hsissen +44 (0)20 7594 6261

 
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Location

 

910BElectrical EngineeringSouth Kensington Campus

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Summary

 

Publications

Citation

BibTex format

@inproceedings{Davis:2018:10.1145/3204919.3204923,
author = {Davis, JJ and Levine, J and Stott, E and Hung, E and Cheung, P and Constantinides, G},
doi = {10.1145/3204919.3204923},
pages = {4:1--4:1},
publisher = {ACM},
title = {KOCL: Kernel-level Power Estimation for Arbitrary FPGA-SoC-accelerated OpenCL Applications},
url = {http://dx.doi.org/10.1145/3204919.3204923},
year = {2018}
}

RIS format (EndNote, RefMan)

TY  - CPAPER
AB - This work presents KOCL, a fully automated tool flow and accompanying software, accessible through a minimalist API, allowing OpenCL developers targetting FPGA-SoC devices to obtain kernel-level power estimates for their applications via function calls in their host code. KOCL is open-source, available with example applications at https://github.com/PRiME-project/KOCL. In order to maximise accessibility, KOCL necessitates no user exposure to hardware whatsoever.
AU - Davis,JJ
AU - Levine,J
AU - Stott,E
AU - Hung,E
AU - Cheung,P
AU - Constantinides,G
DO - 10.1145/3204919.3204923
EP - 1
PB - ACM
PY - 2018///
SP - 4
TI - KOCL: Kernel-level Power Estimation for Arbitrary FPGA-SoC-accelerated OpenCL Applications
UR - http://dx.doi.org/10.1145/3204919.3204923
UR - https://dl.acm.org/citation.cfm?id=3204923
UR - http://hdl.handle.net/10044/1/58759
ER -