Publications
349 results found
Guan Z, Wong JSJ, Chaudhuri S, et al., 2014, Mitigation of process variation effect in FPGAs with partial rerouting method, IEICE ELECTRONICS EXPRESS, Vol: 11, ISSN: 1349-2543
Liu J, Bouganis C, Cheung PYK, 2014, Image Progressive Acquisition for Hardware Systems, Design, Automation and Test in Europe Conference and Exhibition (DATE), Publisher: IEEE, ISSN: 1530-1591
Liu J, Bouganis C, Cheung PYK, 2014, Kernel-based Adaptive Image Sampling, 9th International Conference on Computer Vision Theory and Applications (VISAPP), Publisher: IEEE, Pages: 25-32
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- Citations: 2
Stott E, Guan Z, Levine JM, et al., 2013, Variation and Reliability in FPGAs, IEEE DESIGN & TEST, Vol: 30, Pages: 50-59, ISSN: 2168-2356
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- Citations: 6
Wong JSJ, Cheung PYK, 2013, Timing Measurement Platform for Arbitrary Black-Box Circuits Based on Transition Probability, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol: 21, Pages: 2307-2320, ISSN: 1063-8210
Powell A, Savvas-Bouganis C, Cheung PYK, 2013, High-level power and performance estimation of FPGA-based soft processors and its application to design space exploration, JOURNAL OF SYSTEMS ARCHITECTURE, Vol: 59, Pages: 1144-1156, ISSN: 1383-7621
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- Citations: 10
Guan Z, Wong JSJ, Chaudhuri S, et al., 2013, A VARIATION-ADAPTIVE RETIMING METHOD EXPLOITING RECONFIGURABILITY, 23rd International Conference on Field Programmable Logic and Applications (FPL), Publisher: IEEE, ISSN: 1946-1488
Levine JM, Stott E, Constantinides GA, et al., 2013, SMI: SLACK MEASUREMENT INSERTION FOR ONLINE TIMING MONITORING IN FPGAS, 23rd International Conference on Field Programmable Logic and Applications (FPL), Publisher: IEEE, ISSN: 1946-1488
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- Citations: 1
Guan Z, Wong JSJ, Chaudhuri S, et al., 2013, Exploiting Stochastic Delay Variability on FPGAs with Adaptive Partial Rerouting, 12th International Conference on Field-Programmable Technology (FPT), Publisher: IEEE, Pages: 254-261
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- Citations: 4
Liu J, Bouganis C, Cheung PK, 2013, Domain-specific Progressive Sampling of Face Images, 1st IEEE Global Conference on Signal and Information Processing (GlobalSIP), Publisher: IEEE, Pages: 1021-1024, ISSN: 2376-4066
Chau TCP, Kwok K-W, Chow GCT, et al., 2013, Acceleration of Real-time Proximity Query for Dynamic Active Constraints, 12th International Conference on Field-Programmable Technology (FPT), Publisher: IEEE, Pages: 206-213
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- Citations: 2
Chau TCP, Niu X, Eele A, et al., 2013, Heterogeneous Reconfigurable System for Adaptive Particle Filters in Real-Time Applications, 9th International Applied Reconfigurable Computing Symposium (ARC), Publisher: SPRINGER-VERLAG BERLIN, Pages: 1-12, ISSN: 0302-9743
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- Citations: 11
Chau TCP, Luk W, Cheung PYK, et al., 2012, Adaptive sequential Monte Carlo approach for real-time applications, Pages: 527-530
This paper presents an adaptive Sequential Monte Carlo approach for real-time applications. Sequential Monte Carlo method is employed to estimate the states of dynamic systems using weighted particles. The proposed approach reduces the run-time computation complexity by adapting the size of the particle set. Multiple processing elements on FPGAs are dynamically allocated for improved energy efficiency without violating real-time constraints. A robot localisation application is developed based on the proposed approach. Compared to a non-adaptive implementation, the dynamic energy consumption is reduced by up to 70% without affecting the quality of solutions. © 2012 IEEE.
Levine JM, Stott E, Constantinides GA, et al., 2012, Online Measurement of Timing in Circuits: for Health Monitoring and Dynamic Voltage & Frequency Scaling, 20th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), Publisher: IEEE, Pages: 109-116
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- Citations: 21
Cope B, Cheung PYK, Luk W, et al., 2011, A systematic design space exploration approach to customising multi-processor architectures: Exemplified using graphics processors, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Vol: 6760 LNCS, Pages: 63-83, ISSN: 0302-9743
A systematic approach to customising Homogeneous Multi-Processor (HoMP) architectures is described. The approach involves a novel design space exploration tool and a parameterisable system model. Post-fabrication customisation options for using reconfigurable logic with a HoMP are classified. The adoption of the approach in exploring pre- and post-fabrication customisation options to optimise an architecture's critical paths is then described. The approach and steps are demonstrated using the architecture of a graphics processor. We also analyse on-chip and off-chip memory access for systems with one or more processing elements (PEs), and study the impact of the number of threads per PE on the amount of off-chip memory access and the number of cycles for each output. It is shown that post-fabrication customisation of a graphics processor can provide up to four times performance improvement for negligible area cost. © 2011 Springer-Verlag Berlin Heidelberg.
Cheung PYK, 2011, Introduction to Special Section FPGA 2009, ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS, Vol: 4, ISSN: 1936-7406
Angelopoulou M, Bouganis C-S, Cheung PYK, 2011, Blur Identification with Assumption Validation for Sensor-based Video Reconstruction and its Implementation on FPGA, IET Computers & Digital Techniques
Cheung PYK, Sedcole NP, Wong JS, 2011, Method of Measuring Delay in An Integrated Circuit, US 0095768 A1
A method of measuring signal delay in a integrated circuit comprising applying a common clock signal at a circuit input and output, applying a test signal at the circuit input, detecting a corresponding output signal at the circuit output and detecting whether the test signal and output signal occur in a common part of the clock signal.
Cope B, Cheung PYK, Luk W, et al., 2011, A systematic design space exploration approach to customising multi-processor architectures: Exemplified using graphics processors, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Vol: 6760 LNCS, Pages: 63-83, ISSN: 0302-9743
A systematic approach to customising Homogeneous Multi-Processor (HoMP) architectures is described. The approach involves a novel design space exploration tool and a parameterisable system model. Post-fabrication customisation options for using reconfigurable logic with a HoMP are classified. The adoption of the approach in exploring pre- and post-fabrication customisation options to optimise an architecture's critical paths is then described. The approach and steps are demonstrated using the architecture of a graphics processor. We also analyse on-chip and off-chip memory access for systems with one or more processing elements (PEs), and study the impact of the number of threads per PE on the amount of off-chip memory access and the number of cycles for each output. It is shown that post-fabrication customisation of a graphics processor can provide up to four times performance improvement for negligible area cost. © 2011 Springer-Verlag Berlin Heidelberg.
Wong JSJ, Cheung PYK, 2011, Improved Delay Measurement Method in FPGA based on Transition Probability, 19th Annual ACM International Symposium on Field-Programmable Gate Arrays, Publisher: ASSOC COMPUTING MACHINERY, Pages: 163-172
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- Citations: 2
Mak T, Cheung PYK, Lam KP, et al., 2011, Adaptive routing in network-on-chips using a dynamic-programming network, IEEE Transactions on Industrial Electronics, Vol: 58, Pages: 3701-3716
Levine JM, Stott EA, Constantinides GA, et al., 2011, Health monitoring of live circuits in FPGAs based on time delay measurement (abstract only), Pages: 284-284
Lysaght P, Luk W, Cheung PYK, 2010, Proceedings - 2010 International Conference on Field Programmable Logic and Applications, FPL 2010: Message from the steering committee, Proceedings - 2010 International Conference on Field Programmable Logic and Applications, FPL 2010
Kahoul A, Smith AM, Constantinides GA, et al., 2010, Efficient Heterogeneous Architecture Floorplan Optimization using Analytical Methods, ACM Transactions on Reconfigurable Technology and Systems, Vol:
Wu Y, Kuvinichkul P, Cheung PYK, et al., 2010, Towards Anthropomorphic Robot Thereminist, International Conference on Robotics and Biomimetics (ROBIO), Publisher: IEEE, Pages: 235-240
Theremin is an electronic musical instrument considered to be the most difficult to play which requires the player's hands to have high precision and stability as any position change within proximity of the instrument's antennae can make a difference to the pitch or volume. In a different direction to previous developments of Theremin playing robots, we propose a Humanoid Thereminist System that goes beyond using only one degree of freedom which will open up the possibility for robot to acquire more complex skills, such as aerial fingering and include musical expressions in playing the Theremin. The proposed system consists of two phases, namely calibration phase and playing phase which can be executed independently. During the playing phase, the System takes input from a MIDI file and performs path planning using a combination of minimum energy strategy in joint space and feedback error correction for next playing note. Three experiments have been conducted to evaluate the developed system quantitatively and qualitatively by playing a selection of music files. The experiments have demonstrated that the proposed system can effectively utilise multiple degrees of freedoms while maintaining minimum pitch error margins.
Smith AM, Constantinides GA, Cheung PYK, 2010, An Automated Flow for Arithmetic Component Generation in Field-Programmable Gate Arrays, ACM Transactions on Reconfigurable Technology and Systems, Vol:
Smith AM, Constantinides GA, Cheung PYK, 2010, FPGA Architecture Optimization Using Geometric Programming, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol: 29, Pages: 1163-1176, ISSN: 0278-0070
This paper is concerned with the application of geometric programming to the design of homogeneous field programmable gate array (FPGA) architectures. The paper builds on an increasing body of work concerned with modeling reconfigurable architectures, and presents a full area and delay model of an FPGA. We use a geometric programming framework to show how transistor sizing and high-level architecture parameter selection can now be solved as a concurrent optimization problem. We validate the model through the use of simulation program with integrated circuit emphasis (SPICE) models and the versatile place and route (VPR) FPGA architecture simulation tool. Not only does the optimization framework allow architectures to be optimized orders of magnitude faster than previous work, but the combined optimization can lead to different architectural conclusions compared to conventional methods by exploring the coupling between the two sets of optimization variables. Specifically, we show that as delay takes more significance in the objective of the optimization, there should be more lookup tables in a logic block, whereas conventional techniques suggest that there should be fewer lookup tables in an FPGA logic block.
Cope B, Cheung PYK, Luk W, et al., 2010, Performance comparison of graphics processors to reconfigurable logic: a case study, IEEE Transactions on Computers, Vol: 54, Pages: 433-448, ISSN: 0018-9340
A systematic approach to the comparison of the graphics processor (GPU) and reconfigurable logic is defined in terms of three throughput drivers. The approach is applied to five case study algorithms, characterized by their arithmetic complexity, memory access requirements, and data dependence, and two target devices: the nVidia GeForce 7900 GTX GPU and a Xilinx Virtex-4 field programmable gate array (FPGA). Two orders of magnitude speedup, over a general-purpose processor, is observed for each device for arithmetic intensive algorithms. An FPGA is superior, over a GPU, for algorithms requiring large numbers of regular memory accesses, while the GPU is superior for algorithms with variable data reuse. In the presence of data dependence, the implementation of a customized data path in an FPGA exceeds GPU performance by up to eight times. The trends of the analysis to newer and future technologies are analyzed.
Bouganis C, Pournara I, Cheung PYK, 2010, Exploration of Heterogeneous FPGAs for Mapping Linear Projection Designs, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol: 18
Jamieson P, Becker T, Cheung PYK, et al., 2010, Benchmarking and evaluating reconfigurable architectures targeting the mobile domain, ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol: 15
We present the GroundHog 2009 benchmarking suite that evaluates the power consumption of reconfigurable technology for applications targeting the mobile computing domain. This benchmark suite includes seven designs; one design targets fine-grained FPGA fabrics allowing for quick state-of-the-art evaluation, and six designs are specified at a high level allowing them to target a range of existing and future reconfigurable technologies. Each of the six designs can be stimulated with the help of synthetically generated input stimuli created by an open-source tool included in the downloadable suite. Another tool is included to help verify the correctness of each implemented design. To demonstrate the potential of this benchmark suite, we evaluate the power consumption of two modern industrial FPGAs targeting the mobile domain. Also, we show how an academic FPGA framework, VPR 5.0, that has been updated for power estimates can be used to estimates the power consumption of different FPGA architectures and an open-source CAD flow mapping to these architectures.
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