11 results found
Wilton S, Ho C, Quinton B, et al., 2008, A Synthesizable Datapath-Oriented Embedded FPGA Fabric for Silicon Debug Applications, ACM Transactions on Reconfigurable Technology and Systems, Vol: 1, Pages: 1-25
We present an architecture for a synthesizable datapath-oriented FPGA core which can be used to provide post-fabrication flexibility to an SoC. Our architecture is optimized for bus-based operations and employs a directional routing architecture, which allows it to be synthesized using standard ASIC design tools and flows. The primary motivation for this architecture is to provide an efficient mechanism to support on-chip debugging. The fabric can also be used to implement other datapath-oriented circuits such as those needed in signal processing and computation-intensive applications. We evaluate our architecture using a set of benchmark circuits and compare it to previous fabrics in terms of area, speed, and power consumption.\r\n\r\n
Ho C, Yu C, Leong P, et al., 2007, Domain-Specific FPGA: Architecture and Floating Point Applications, International Conference on Field Programmable Logic and Applications (FPL), Pages: 196-201
This paper presents a novel architecture for domain-specific FPGA devices. This architecture can be optimised for both speed and density by exploiting domain-specific information to produce efficient reconfigurable logic with multiple granularity. In the reconfigurable logic, general-purpose fine-grained units are used for implementing control logic and bit-oriented operations, while domain-specific coarse-grained units and heterogeneous blocks are used for implementing datapaths; the precise amount of each type of resources can be customised to suit specific application domains. Issues and challenges associated with the design flow and the architecture modelling are addressed. Examples of the proposed architecture for speeding up floating point applications are illustrated. Current results indicate that the proposed architecture can achieve 2.5 times improvement in speed and 18 times reduction in area on average, when compared with traditional FPGA devices on selected floating point benchmark circuits.
Chun Hok Ho, Chi Wai Yu, Philip Leong, et al., 2007, Domain-specific hybrid FPGA: architecture and floating point applications, Amsterdam, International Workshop on Field Programmable Logic and Applications (FPL), Publisher: IEEE, Pages: 196-201
Leff D, Koh P, Aggarwal R, et al., 2006, Optical Mapping of the Frontal Cortex During a Surgical Knot-Tying Task: A Feasibility Study, Medical Image Computing and Computer Aided Intervention - MICCAI 2006, Pages: 141-148
Chow CT, Tsui LSM, Leong PHW, et al., 2005, Dynamic voltage scaling for commercial FPGAs, International Conference on Field Programmable Technology (FPT), Pages: 173-180
Leong MP, Cheung CC, Cheung CW, et al., 2005, CPE: a parallel library for financial engineering applications, Computer, Vol: 38, Pages: 70-77, ISSN: 0018-9162
Leong P, 2005, A Parallel Library for Financial Engineering Applications, Vol: 38, Pages: 70-77
The Clustertech parallel environment is an object-oriented C++ library\r\nthat uses abstractions to simplify parallel programming for financial\r\nengineering applications. The message passing interface ensures CPEÆs\r\nportability and performance over a wide range of parallel cluster and\r\nsymmetric multiprocessing machines.
Lee DU, Luk W, Villasenor JD, et al., 2005, A hardware Gaussian noise generator using the Wallace method, IEEE Transactions on VLSI Systems, Vol: 13, Pages: 911-920, ISSN: 1063-8210
MP Leong, 2003, A Variable-Radix Digit-Serial DesignMethodology and its Application to the Discrete Cosine Transform, IEEE Transactions on VLSI Systems, Vol: 11, Pages: 90-104, ISSN: 1063-8210
Leong PHW, Leung IKH, 2002, A microcoded elliptic curve processor using FPGA technology, IEEE Transactions on VLSI Systems, Vol: 10, Pages: 550-559, ISSN: 1063-8210
Leong P, 2001, Pilchard - A Reconfigurable Computing Platform with Memory Slot Interface, IEEE Symposium on Field-Programmable Custom Computing Machines, Publisher: IEEE Computer Soc, Pages: 170-179
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