Imperial College London

DR Shuanglong Liu

Faculty of EngineeringDepartment of Computing

Research Associate



+44 (0)7784 105 508s.liu13 Website CV




572Huxley BuildingSouth Kensington Campus





Shuanglong Liu is a Research Associate in the Department of Computing's Custom Computing group at Imperial College London. He currently researched on the project of Accelerating Machine Learning and Machine Learning for Accelerator Design.

He obtained the PhD degree under Dr. Christos Bouganis's supervisor in the Department of Electrical and Electronic Engineering's Circuits and Systems group at Imperial College LondonHis research was funded by Imperial President's PhD Scholarship. He received the B.S and M.S degrees from the Department of Electronic Engineering, Tsinghua University, Beijing, China, in 2010 and 2013 respectively.

Shuanglong's research directions are mainly focused on the hardware accelerations for Deep Neural Networks and Statistical Inference problems using FPGAs and GPUs. Below is some of the most recent work:

  • FPGA-based Acceleration for Convolutional Neural Network Based Segmentation
  • Acceleration of computationally intensive Sequential Monte Carlo (SMC) methods using FPGAs
  • Precision optimization of Markov Chain Monte Carlo (MCMC) methods
  • Use of MCMC/SMC hardware accelerators for large data applications

Selected Publications

Journal Articles

Liu S, Fan H, Niu X, et al., 2018, Optimizing CNN-based segmentation with deeply customized convolutional and deconvolutional architectures on FPGA, ACM Transactions on Reconfigurable Technology and Systems, Vol:11, ISSN:1936-7406

Liu S, Mingas G, Bouganis C, 2016, An Unbiased MCMC FPGA-based Accelerator in the Land of Custom Precision Arithmetic, IEEE Transactions on Computers, Vol:66, ISSN:0018-9340, Pages:745-758

Liu S, Zhang C, Huang Y, et al., A Time Difference Measurement and Clock Synchronization Technology Based on Interpolating Sampling, Journal of Circuits and Systems, ISSN:1007-0249


Liu S, Chu RSW, Wang X, et al., 2019, Optimizing CNN-Based Hyperspectral Image Classification on FPGAs, Pages:17-31, ISSN:0302-9743

Ng H-C, Liu S, Luk W, 2018, ADAM: Automated Design Analysis and Merging for Speeding up FPGA Development., FPGAInternational Symposium on Field Programmable Gate Arrays, ACM, Pages:189-198

Liu S, Bouganis CS, 2017, Communication-aware MCMC method for big data applications on FPGAs, Pages:9-16

Liu S, Mingas G, Bouganis C-S, 2015, An Exact MCMC Accelerator Under Custom Precision Regimes, International Conference on Field Programmable Technology (FTP), IEEE, Pages:120-127

Liu S, Mingas G, Bouganis C-S, 2014, Parallel Resampling for Particle Filters on FPGAs, International Conference on Field Programmable Technology, IEEE, Pages:191-198

More Publications