Publications
17 results found
Williams I, Brunton E, Rapeaux A, et al., 2020, SenseBack-an implantable system for bidirectional neural interfacing, IEEE Transactions on Biomedical Circuits and Systems, Vol: 14, Pages: 1079-1087, ISSN: 1932-4545
Chronic in-vivo neurophysiology experiments require highly miniaturized, remotely powered multi-channel neural interfaces which are currently lacking in power or flexibility post implantation. In this article, to resolve this problem we present the SenseBack system, a post-implantation reprogrammable wireless 32-channel bidirectional neural interfacing that can enable chronic peripheral electrophysiology experiments in freely behaving small animals. The large number of channels for a peripheral neural interface, coupled with fully implantable hardware and complete software flexibility enable complex in-vivo studies where the system can adapt to evolving study needs as they arise. In complementary ex-vivo and in-vivo preparations, we demonstrate that this system can record neural signals and perform high-voltage, bipolar stimulation on any channel. In addition, we demonstrate transcutaneous power delivery and Bluetooth 5 data communication with a PC. The SenseBack system is capable of stimulation on any channel with ±20 V of compliance and up to 315 μA of current, and highly configurable recording with per-channel adjustable gain and filtering with 8 sets of 10-bit ADCs to sample data at 20 kHz for each channel. To the best of our knowledge this is the first such implantable research platform offering this level of performance and flexibility post-implantation (including complete reprogramming even after encapsulation) for small animal electrophysiology. Here we present initial acute trials, demonstrations and progress towards a system that we expect to enable a wide range of electrophysiology experiments in freely behaving animals.
Luan S, Williams I, Maslik M, et al., 2018, Compact standalone platform for neural recording with real-time spike sorting and data logging, Journal of Neural Engineering, Vol: 15, Pages: 1-13, ISSN: 1741-2552
Objective. Longitudinal observation of single unit neural activity from largenumbers of cortical neurons in awake and mobile animals is often a vital step in studying neural network behaviour and towards the prospect of building effective Brain Machine Interfaces (BMIs). These recordings generate enormous amounts of data for transmission & storage, and typically require o ine processing to tease out the behaviour of individual neurons. Our aim was to create a compact system capable of: 1) reducing the data bandwidth by circa 2 to 3 orders of magnitude (greatly improving battery lifetime and enabling low power wireless transmission in future versions); 2) producing real-time, low-latency, spike sorted data; and 3) long term untethered operation. Approach. We have developed a headstage that operates in two phases. In the short training phase a computer is attached and classic spike sorting is performed to generate templates. In the second phase the system is untethered and performs template matching to create an event driven spike output that is logged to a micro-SD card. To enable validation the system is capable of logging the high bandwidth raw neural signal data as well as the spike sorted data. Main results. The system can successfully record 32 channels of raw neural signal data and/or spike sorted events for well over 24 hours at a time and is robust to power dropouts during battery changes as well as SD card replacement. A 24-hour initial recording in a nonhuman primate M1 showed consistent spike shapes with the expected changes in neural activity during awake behaviour and sleep cycles. Signi cance The presented platform allows neural activity to be unobtrusively monitored and processed in real-time in freely behaving untethered animals { revealing insights that are not attainable through scheduled recording sessions. This system achieves the lowest power per channel to date and provides a robust, low-latency, low-bandwidth and veri able output suitable f
Liu Y, Luan S, Williams I, et al., 2017, A 64-Channel Versatile Neural Recording SoC with Activity Dependant Data Throughput, IEEE Transactions on Biomedical Circuits and Systems, Vol: 11, Pages: 1344-1355, ISSN: 1932-4545
Modern microtechnology is enabling the channel count of neural recording integrated circuits to scale exponentially. However, the raw data bandwidth of these systems is increasing proportionately, presenting major challenges in terms of power consumption and data transmission (especially for wireless systems). This paper presents a system that exploits the sparse nature of neural signals to address these challenges and provides a reconfigurable low-bandwidth event-driven output. Specifically, we present a novel 64-channel low noise (2.1μVrms, low power (23μW per analogue channel) neural recording system-on-chip (SoC). This features individually-configurable channels, 10-bit analogue-to-digital conversion, digital filtering, spike detection, and an event-driven output. Each channel's gain, bandwidth & sampling rate settings can be independently configured to extract Local Field Potentials (LFPs) at a low data-rate and/or Action Potentials (APs) at a higher data rate. The sampled data is streamed through an SRAM buffer that supports additional on-chip processing such as digital filtering and spike detection. Real-time spike detection can achieve ~2 orders of magnitude data reduction, by using a dual polarity simple threshold to enable an event driven output for neural spikes (16-sample window). The SoC additionally features a latency-encoded asynchronous output that is critical if used as part of a closed-loop system. This has been specifically developed to complement a separate on-node spike sorting co-processor to provide a real-time (low latency) output. The system has been implemented in a commercially-available 0.35μm CMOS technology occupying a silicon area of 19.1mm² (0.3mm² gross per channel), demonstrating a low power & efficient architecture which could be further optimised by aggressive technology and supply voltage scaling.
Luan S, Williams I, Maslik M, et al., 2017, Compact Standalone Platform for Neural Recording with Real-Time Spike Sorting and Data Logging
<jats:p>Objective. Longitudinal observation of single unit neural activity from large numbers of cortical neurons in awake and mobile animals is often a vital step in studying neural network behaviour and towards the prospect of building effective Brain Machine Interfaces (BMIs). These recordings generate enormous amounts of data for transmission & storage, and typically require offline processing to tease out the behaviour of individual neurons. Our aim was to create a compact system capable of: 1) reducing the data bandwidth by circa 3 orders of magnitude (greatly improving battery lifetime and enabling low power wireless transmission); 2) producing real-time, low-latency, spike sorted data; and 3) long term untethered operation. Approach. We have developed a headstage that operates in two phases. In the short training phase a computer is attached and classic spike sorting is performed to generate templates. In the second phase the system is untethered and performs template matching to create an event driven spike output that is logged to a micro-SD card. To enable validation the system is capable of logging the high bandwidth raw data as well as the spike sorted data. Main results. The system can successfully record 32 channels of raw and/or spike sorted data for well over 24 hours at a time and is robust to power dropouts during battery changes as well as SD card replacement. A 24-hour initial recording in a non-human primate M1 showed consistent spike shapes with the expected changes in neural activity during awake behaviour and sleep cycles. Significance The presented platform allows neural activity to be unobtrusively monitored and processed in real-time in freely behaving untethered animals revealing insights that are not attainable through scheduled recording sessions and provides a robust, low-latency, low-bandwidth output suitable for BMIs, closed loop neuromodulation, wireless transmission and long term data logging.</jats:p>
Williams I, Rapeaux A, Liu Y, et al., 2017, A 32-channel bidirectional neural/EMG interface with on-chip spike detection for sensorimotor feedback, IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 528-531
This paper presents a novel 32-channel bidirectional neural interface, capable of high voltage stimulation and low power, low-noise neural recording. Current-controlled biphasic pulses are output with a voltage compliance of 9.25V, user configurable amplitude (max. 315 uA) & phase duration (max. 2 ms). The low-voltage recording amplifiers consume 23 uW per channel with programmable gain between 225 - 4725. Signals are10-bit sampled at 16 kHz. Data rates are reduced by granular control of active recording channels, spike detection and event-driven communication, and repeatable multi-pulse stimulation configurations.
Luan S, Liu Y, Williams I, et al., 2017, An Event-Driven SoC for Neural Recording, IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 404-407
This paper presents a novel 64-channel ultra-low power/low noise neural recording System-on-Chip (SoC) featuring a highly reconfigurable Analogue Front-End (AFE) and block-selectable data-driven output. This allows a tunable bandwidth/sampling rate for extracting Local Field Potentials (LFPs)and/or Extracellular Action Potentials (EAPs). Realtime spike detection utilises a dual polarity simple threshold to enable an event driven output for neural spikes (16-sample window). The 64-channels are organised into 16 sets of 4-channel recording blocks, with each block having a dedicated 10-bit SAR ADC that is time division multiplexed among the 4 channels. Eachchannel can be individually powered down and configured for bandwidth, gain and detection threshold. The output can thus combine continuous-streaming and event-driven data packets with the system configured as SPI slave. The SoC is implemented in a commercially-available 0.35u m CMOS technology occupying a silicon area of 19.1mm^2 (0.3mm^2 gross per channel) and requiring 32uW/channel power consumption (AFE only).
Luan S, Williams I, de Carvalho F, et al., 2016, Next Generation Neural Interfaces for low-power multichannel spike sorting, FENS Forum of Neuroscience, Publisher: FENS
Williams I, Luan S, Jackson A, et al., 2015, A scalable 32 channel neural recording and real-time FPGA based spike sorting system, IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 187-191
This demo presents a scalable a 32-channel neuralrecording platform with real-time, on-node spike sorting ca-pability. The hardware consists of: an Intan RHD2132 neuralamplifier; a low power Igloo ® nano FPGA; and an FX3 USB3.0 controller. Graphical User Interfaces for controlling thesystem, displaying real-time data, and template generation witha modified form of WaveClus are demonstrated.
Williams I, Luan S, Jackson A, et al., 2015, Live Demonstration: A Scalable 32-Channel Neural Recording and Real-time FPGA Based Spike Sorting System, 11th IEEE Annual Biomedical Circuits and Systems Conference (BioCAS), Publisher: IEEE, Pages: 187-187, ISSN: 2163-4025
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Luan S, Williams I, Constandinou TG, et al., 2014, Neuromodulation: present and emerging methods, Frontiers of Neuroengineering, Vol: 7, ISSN: 1662-6443
Neuromodulation has wide ranging potential applications in replacing impaired neural function (prosthetics), as a novel form of medical treatment (therapy), and as a tool for investigating neurons and neural function (research). Voltage and current controlled electrical neural stimulation (ENS) are methods that have already been widely applied in both neuroscience and clinical practice for neuroprosthetics. However, there are numerous alternative methods of stimulating or inhibiting neurons. This paper reviews the state-of-the-art in ENS as well as alternative neuromodulation techniques - presenting the operational concepts, technical implementation and limitations - in order to inform system design choices.
Luan S, Constandinou TG, 2014, A Charge-Metering Method for Voltage-Mode Neural Stimulation, Journal of Neuroscience Methods, Vol: 224, Pages: 39-47, ISSN: 0165-0270
Electrical Neural Stimulation is the technique used to modulate neural activity by inducing an instantaneous charge imbalance. This is typically achieved by injecting a constant current and controlling the stimulation time. However, constant voltage stimulation is found to be more energy-efficient although it is challenging to control the amount of charge delivered. This paper presents a novel, fully-integrated circuit for facilitating charge-metering in constant voltage stimulation. It utilises two complementary stimulation paths. Each path includes a small capacitor, a comparator and a counter. They form a mixed-signal integrator that integrates the stimulation current onto the capacitor whilst monitoring its voltage against a threshold using the comparator. The pulses from the comparator are used to increment the counter and reset the capacitor. Therefore, by knowing the value of the capacitor, threshold voltage and output of the counter, the quantity of charge delivered can be calculated. The system has been fabricated in 0.18μm CMOS technology, occupying a total active area of 339μm×110μm. Experimental results were taken using: (1) a resistor-capacitor EEI model and (2) platinum electrodes with ringer solution. The viability of this method in recruiting action potentials has been demonstrated using a cuff electrode with Xenopus Sciatic nerve. For a 10nC target charge delivery, the results of (2) show a charge delivery error of 3.4% and a typical residual charge of 77.19pC without passive charge recycling. The total power consumption is 45μW. The performance is comparable with other publications. Therefore, the proposed stimulation method can be used as a new approach for neural stimulation.
Leene LB, Luan S, Constandinou TG, 2013, A 890fJ/bit UWB transmitter for SOC integration inhigh bit-rate transcutaneous bio-implants, IEEE International Symposium on Circuits and Systems (ISCAS)
The paper presents a novel ultra low power UWBtransmitter system for near field communication in transcutaneous biotelemetries. The system utilizes an all-digital architecture based on minising the energy dissipated per bit transmitted by efficiently encoding a packet of pulses with multiple bits and utilizing oscillator referenced delays. This is achieved by introducing a novel bi-phasic 1.65 pJ per pulse UWB pulse generator together with a 72uμW DCO that provide a transmission bandwidth of 77.5 Mb/s with an energy efficiency of 890fJ per bit from a 1.2V supply. The circuit core occupies a compact silicon footprint of 0.026mm2 in a 0.18 μm CMOS technology.
Guilvard A, Eftekhar A, Luan S, et al., 2012, A Fully-Programmable Neural Interface for Multi-Polar, Multi-Channel Stimulation Strategies, International Symposium on Circuits and Systems (ISCAS), ISSN: 0271-4302
This paper describes a novel integrated electrodeinterface for multi-polar stimulation of multi-electrode arrays. This interface allows for simultaneous stimulation using multiple electrodes configured as source or sink with different phase and amplitudes in order to perform field shaping inside the tissue. The system is designed in an high voltage 0.18 μm CMOS process with 8 channels. It features an output voltage swing of 16V and current up to 0.5mA for electrode impedences of up to 30kΩ which is suitable for cuff and cortical grid arrays. This electrode interface comprise a digital module which stores stimulation settings and operates the different electrode channels. Here we present the full system architecture and simulation results.
Luan S, Constandinou TG, 2012, A Novel Charge-Metering Method for Voltage Mode Neural Stimulation, International Symposium on Circuits and Systems (ISCAS), ISSN: 0271-4302
This paper presents a novel, fully-integrated circuit for achieving change-balanced voltage-mode neural stimulation based on a charge-metering technique. The proposed system uses two small on-chip capacitors, a counter, two comparators and a control-logic circuit to measure the charge delivered to the tissue. The circuit has been designed to deliver a maximum charge of 10.24nC to the tissue within 100us. It is shown that the charge delivery error is 0.4-4% with a maximum residual charge of -73pC. Implemented in a standard 0.18um CMOS technology, the total power consumption is 42uW (excluding stimulus).
Mirza KB, Luan S, Constandinou TG, 2012, Towards a Fully-Integrated Solution for Capacitor-Based Neural Stimulation, International Symposium on Circuits and Systems (ISCAS), ISSN: 0271-4302
Charge-mode stimulation (ChgMS) is a relatively new method being explored in the field of electrical neural stimulation. One of the key challenges in such a system is to overcome charge sharing between the storage capacitor and the double layer capacitor in the Electrode-Electrolyte-Interface (EEI). In this work, this issue is overcome by using a second-generation negative current conveyor (CCII-) with low current tracking error. The level of charge sharing in the circuit is expressed by a new figure of merit (charge delivery efficiency) introduced in this paper. The proposed system has a maximum power efficiency of 76.6% and a total power consumption of 270uW per electrode for a target charge stimulus of 0.9nC. Crucially, the system achieves a minimum charge delivery efficiency of 98.22%.
Luan S, Eftekhar A, Murphy O, et al., 2011, Towards an Inductively Coupled Power/Data Link for Bondpad-Less Silicon Chips, IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 7-10
This paper explores the concept of developing a bondpad-less fullyintegrated inductive link for power/data transfer between a silicon chip and a PCB. A key feature of the implemented system is that it requires no off-chip components. The proposed chip uses a standard 0.35um process and occupies an area of 2.5 x 2.5 mm^2. 9mW power was designed to be obtained on-chip through 900MHz carrier wave. Binary Phase Shift Keying (BPSK) and Load shift keying (LSK) are used for the the PCB-to-chip and chip-to-PCB link respectively for half-duplex communication.
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