Imperial College London

DrThomasClarke

Faculty of EngineeringDepartment of Electrical and Electronic Engineering

Principal Teaching Fellow of Technological Transformation
 
 
 
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Contact

 

+44 (0)20 7594 6257t.clarke

 
 
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Assistant

 

Mrs Wiesia Hsissen +44 (0)20 7594 6261

 
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Location

 

615Electrical EngineeringSouth Kensington Campus

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Summary

 

Publications

Publication Type
Year
to

15 results found

Haigh D G, Clarke, T J W, Udenwa Aet al., 2006, Towards symbolic CAD for active circuits with true synnthesis capability, Pages: 1-6

Conference paper

Haigh DG, Clarke TJW, Radmore PM, 2006, Symbolic framework for linear active circuits based on port equivalence using limit variables, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, Vol: 53, Pages: 2011-2024, ISSN: 1549-8328

Journal article

Haigh D G, Clarke, T J W, Radmore P Met al., 2006, Symbolic framework for linear active circuits based on port equivalence using limit variables, IEEE Transactons on Circuits and Systems I (Regular papers), Vol: 53, Pages: 2011-2024, ISSN: 1558-0806

Journal article

Haigh DG, Clarke TJW, Radmore PM, 2006, A mathematical framework for active circuits based on port equivalence using limit variables, IEEE International Symposium on Circuits and Systems (ISCAS 2006), 21 - 24 May 2006, island of Kos, Greece, Publisher: IEEE, Pages: 2949-2952

Conference paper

Androutsopoulos V, Brookes DM, Clarke TJW, 2004, Protocol converter synthesis, IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES, Vol: 151, Pages: 391-401, ISSN: 1350-2387

Journal article

Androutsopoulos V, Clarke TJW, Brookes DM, 2003, Synthesis and optimization of interfaces between hardware modules with incompatible protocols, New York, IEEE international symposium on circuits and systems, Bangkok, Thailand, 25 - 28 May 2003, Publisher: IEEE, Pages: 613-616

Conference paper

Androutsopoulos V, Clarke TJW, Brookes DM, 2003, Synthesis and optimization of interfaces between hardware modules with incompatible protocols, New York, International Symposium on Circuits and Systems, 2003.(ISCAS 2003) Bangkok, Thailand, 25 - 28 May 2003, Publisher: IEEE, Pages: V-613-V-616

Conference paper

Hettiaratchi S, Cheung PYK, Clarke TJW, 2002, Performance-area trade-off of address generators for address decoder- decoupled memory, Los Alamitos, Design, Automation and Test in Europe Conference and Exhibition (2002), Paris, France, 4 - 8 March 2002, Publisher: IEEE Computer Soc, Pages: 902-908

Conference paper

Hettiaratchi S, Cheung PYK, Clarke TJW, 2002, Performance-area trade-off of address generators for address decoder- decoupled memory, Los Alamitos, Design, automation and test in europe conference and exhibition (DATE 2002), Paris, France, 4 - 8 March 2002, Publisher: IEEE Computer Soc, Pages: 902-908

Conference paper

Hettiaratchi S, Cheung PYK, Clarke TJW, 2002, Energy efficient address assignment through minimized memory row switching, New York, IEEE/ACM International Conference on Computer Aided Design, 2002.(ICCAD 2002), San Jose, California, 10 - 14 November 2002, Publisher: IEEE, Pages: 577-581

Conference paper

Hettiaratchi S, Cheung PY, Clarke TJW, 2002, Energy efficient address assignment through minimized memory row switching, New York, International conference on computer-aided design, San Jose, California, 10 - 14 November 2002, Publisher: IEEE, Pages: 577-581

Conference paper

Demirel H, Clarke TJW, Cheung PYK, 1997, Automatic segmentation of training set for facial feature detection, 1997 International Conference on Information, Communications and Signal Processing - Trends in Information Systems Engineering and Wireless Multimedia Communications, Publisher: IEEE, Pages: 984-988

Conference paper

Albaharna OT, Cheung PYK, Clarke TJ, 1996, On the viability of FPGA-based integrated coprocessors, IEEE Symposium on FPGAs for Custom Computing Machines, Publisher: I E E E, COMPUTER SOC PRESS, Pages: 206-215

Conference paper

Demirel H, Clarke T, Cheung PYK, 1996, Adaptive automatic facial feature segmentation, Proceedings of the Second International Conference on Automatic Face and Gesture Recognition (Cat. No. 96TB100079), Pages: 277-282

Conference paper

ALBAHARNA OT, CHEUNG PYK, CLARKE TJ, 1994, AREA & TIME LIMITATIONS OF FPGA-BASED VIRTUAL HARDWARE, 1994 IEEE International Conference on Computer Design - VLSI in Computers and Processors (ICCD 94), Publisher: I E E E, COMPUTER SOC PRESS, Pages: 184-189, ISSN: 1063-6404

Conference paper

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