231 results found
Huang J, Stathopoulos S, Serb A, et al., 2022, NeuroPack: An Algorithm-Level Python-Based Simulator for Memristor-Empowered Neuro-Inspired Computing, Frontiers in Nanotechnology, Vol: 4
Emerging two-terminal nanoscale memory devices, known as memristors, have demonstrated great potential for implementing energy-efficient neuro-inspired computing architectures over the past decade. As a result, a wide range of technologies have been developed that, in turn, are described via distinct empirical models. This diversity of technologies requires the establishment of versatile tools that can enable designers to translate memristors’ attributes in novel neuro-inspired topologies. In this study, we present NeuroPack, a modular, algorithm-level Python-based simulation platform that can support studies of memristor neuro-inspired architectures for performing online learning or offline classification. The NeuroPack environment is designed with versatility being central, allowing the user to choose from a variety of neuron models, learning rules, and memristor models. Its hierarchical structure empowers NeuroPack to predict any memristor state changes and the corresponding neural network behavior across a variety of design decisions and user parameter options. The use of NeuroPack is demonstrated herein via an application example of performing handwritten digit classification with the MNIST dataset and an existing empirical model for metal-oxide memristors.
Antoniou G, Yuan P, Koutsokeras L, et al., 2022, Low-power supralinear photocurrent generation via excited state fusion in single-component nanostructured organic photodetectors, JOURNAL OF MATERIALS CHEMISTRY C, Vol: 10, Pages: 7575-7585, ISSN: 2050-7526
Panidi J, Georgiadou DG, Schoetz T, et al., 2022, Advances in Organic and Perovskite Photovoltaics Enabling a Greener Internet of Things, ADVANCED FUNCTIONAL MATERIALS, Vol: 32, ISSN: 1616-301X
Abbey T, Giotis C, Serb A, et al., 2022, Thermal Effects on Initial Volatile Response and Relaxation Dynamics of Resistive RAM Devices, IEEE ELECTRON DEVICE LETTERS, Vol: 43, Pages: 386-389, ISSN: 0741-3106
Simanjuntak FM, Panidi J, Talbi F, et al., 2022, Formation of a ternary oxide barrier layer and its role in switching characteristic of ZnO-based conductive bridge random access memory devices, APL Materials, Vol: 10
The insertion of a metal layer between an active electrode and a switching layer leads to the formation of a ternary oxide at the interface. The properties of this self-formed oxide are found to be dependent on the Gibbs free energy of oxide formation of the metal (ΔGf°). We investigated the role of various ternary oxides in the switching behavior of conductive bridge random access memory (CBRAM) devices. The ternary oxide acts as a barrier layer that can limit the mobility of metal cations in the cell, promoting stable switching. However, too low (higher negative value) ΔGf° leads to severe trade-offs; the devices require high operation current and voltages to exhibit switching behavior and low memory window (on/off) ratio. We propose that choosing a metal layer having appropriate ΔGf° is crucial in achieving reliable CBRAM devices.
Aivali S, Yuan P, Panidi J, et al., 2022, Electron Transporting Perylene Diimide-Based Random Terpolymers with Variable Co-Monomer Feed Ratio: A Route to All-Polymer Based Photodiodes, MACROMOLECULES, Vol: 55, Pages: 672-683, ISSN: 0024-9297
Yang F, Serb A, Prodromakis T, 2022, Measured behaviour of a memristor-based tuneable instrumentation amplifier, Electronics Letters, ISSN: 0013-5194
A memristor-based tuneable instrumentation amplifier whose gain value can be adjusted by memristor is implemented and measured. While memristive devices are suitable for implementing reconfigurable circuit designs, their non-linear characteristic and parasitic capacitance can impact performance. In this work, an instrumentation amplifier is built on breadboard using off-the-shelf OpAmps and packaged memristor devices and its performance is assessed. Results are compared with an identical design that preplaces memristors with resistors (losing reconfigurability in the process), to reveal the effects arising from the memristor's characteristics. Effects on frequency response, common mode rejection ratio (CMRR) and total harmonic distortion plus noise (THD+N) are observed. The memristor-based instrumentation amplifier begins to be affected by the non-linearity of the device only when the base OpAmps have a THD value below 0.3%. The bandwidth of the instrumentation amplifier is limited by the parasitic capacitance of memristors, and CMRR has small variation when using memristor to replace the original gain resistor. The THD+N value is large compared with identical design, but it is also found that by applying multiple memristors the increasing of THD+N can be relieved.
Maheshwari S, Serb A, Papavassiliou C, et al., 2022, An Adiabatic Capacitive Artificial Neuron With RRAM-Based Threshold Detection for Energy-Efficient Neuromorphic Computing, IEEE Transactions on Circuits and Systems I: Regular Papers, ISSN: 1549-8328
In the quest for low power, bio-inspired computation both memristive and memcapacitive-based Artificial Neural Networks (ANN) have been the subjects of increasing focus for hardware implementation of neuromorphic computing. One step further, regenerative capacitive neural networks, which call for the use of adiabatic computing, offer a tantalising route towards even lower energy consumption, especially when combined with ‘memimpedace’ elements. Here, we present an artificial neuron featuring adiabatic synapse capacitors to produce membrane potentials for the somas of neurons; the latter implemented via dynamic latched comparators augmented with Resistive Random-Access Memory (RRAM) devices. Our initial 4-bit adiabatic capacitive neuron proof-of-concept example shows 90% synaptic energy saving. At 4 synapses/soma we already witness an overall 35% energy reduction. Furthermore, the impact of process and temperature on the 4-bit adiabatic synapse shows a maximum energy variation of 30% at <inline-formula> <tex-math notation="LaTeX">$100^oC$</tex-math> </inline-formula> across the corners without any functionality loss. Finally, the efficacy of our adiabatic approach to ANN is tested for 512 & 1024 synapse/neuron for worst and best case synapse loading conditions and variable equalising capacitance’s quantifying the expected trade-off between equalisation capacitance and range of optimal power-clock frequencies vs. loading (i.e. the percentage of active synapses).
Simanjuntak FM, Hsu C-L, Abbey T, et al., 2021, Conduction channel configuration controlled digital and analog response in TiO2-based inorganic memristive artificial synapses, APL MATERIALS, Vol: 9, ISSN: 2166-532X
Lanza M, Waser R, Ielmini D, et al., 2021, Standards for the Characterization of Endurance in Resistive Switching Devices, ACS Nano, Vol: 15, Pages: 17214-17231, ISSN: 1936-0851
Resistive switching (RS) devices are emerging electronic components that could have applications in multiple types of integrated circuits, including electronic memories, true random number generators, radiofrequency switches, neuromorphic vision sensors, and artificial neural networks. The main factor hindering the massive employment of RS devices in commercial circuits is related to variability and reliability issues, which are usually evaluated through switching endurance tests. However, we note that most studies that claimed high endurances >106 cycles were based on resistance versus cycle plots that contain very few data points (in many cases even <20), and which are collected in only one device. We recommend not to use such a characterization method because it is highly inaccurate and unreliable (i.e., it cannot reliably demonstrate that the device effectively switches in every cycle and it ignores cycle-to-cycle and device-to-device variability). This has created a blurry vision of the real performance of RS devices and in many cases has exaggerated their potential. This article proposes and describes a method for the correct characterization of switching endurance in RS devices; this method aims to construct endurance plots showing one data point per cycle and resistive state and combine data from multiple devices. Adopting this recommended method should result in more reliable literature in the field of RS technologies, which should accelerate their integration in commercial products.
Maheshwari S, Stathopoulos S, Wang J, et al., 2021, Design flow for hybrid CMOS/memristor systems--Part I: modeling and verification steps, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol: 68, Pages: 4862-4875, ISSN: 1549-8328
Memristive technology has experienced explosive growth in the last decade, with multiple device structures being developed for a wide range of applications. However, transitioning the technology from the lab into the marketplace requires the development of an accessible and user-friendly design flow, supported by an industry-grade toolchain. In this work, we demonstrate the behaviour of our in-house fabricated custom memristor model and its integration into the Cadence Electronic Design Automation (EDA) tools for verification. Various input stimuli were given to record the memristive device characteristics both at the device level as well as the schematic level for verification of the memristor model. This design flow from device to industrial level EDA tools is the first step before the model can be used and integrated with Complementary Metal-Oxide Semiconductor (CMOS) in applications for hybrid memristor/CMOS system design.
Maheshwari S, Stathopoulos S, Wang J, et al., 2021, Design flow for hybrid CMOS/memristor systems--Part II: circuit schematics and layout, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol: 68, Pages: 4876-4888, ISSN: 1549-8328
\normalsize The capability of in-memory computation, reconfigurability, low power operation as well as multistate operation of the memristive device deems them a suitable candidate for designing electronic circuits with a broad range of applications. Besides, the integrability of memristor with CMOS enables it to use in logic circuits too. In this work, we demonstrate with examples the design flow for memristor-based electronics, after the custom memristor model already being integrated and validated into our chosen Computer-Aided Design (CAD) tool to performing layout-versus-schematic and post-layout checks including the memristive device. We envisage that this step-by-step guide to introducing memristor into the standard integrated circuit design flow will be a useful reference document for both device developers who wish to benchmark their technologies and circuit designers who wish to experiment with memristive-enhanced systems.
Manouras V, Stathopoulos S, Serb A, et al., 2021, Technology agnostic frequency characterization methodology for memristors, SCIENTIFIC REPORTS, Vol: 11, ISSN: 2045-2322
Vaidya D, Kothari S, Abbey T, et al., 2021, Compact Modeling of the Switching Dynamics and Temperature Dependencies in TiOx Memristors-Part II: Physics-Based Model, IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol: 68, Pages: 4885-4890, ISSN: 0018-9383
Vaidya D, Kothari S, Abbey T, et al., 2021, Compact Modeling of the Switching Dynamics and Temperature Dependencies in TiOx-Based Memristors - Part I: Behavioral Model, IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol: 68, Pages: 4877-4884, ISSN: 0018-9383
Serb A, Khiat A, Prodromakis T, 2021, Practical demonstration of a RRAM memory fuse, International Journal of Circuit Theory and Applications, Vol: 49, Pages: 2363-2372, ISSN: 0098-9886
Since its inception, the resistive random access memory (RRAM) fuse has been a good example of how small numbers of RRAM devices can be combined to obtain useful behaviors unachievable by individual devices. In this work, we link the RRAM fuse concept with that of the complementary resistive switch (CRS), exploit that link to experimentally demonstrate a practical RRAM fuse using TiOx-based RRAM cells, and explain its basic operational principles. The fuse is stimulated by trains of identical pulses where successive pulse trains feature opposite polarities. In response, we observe a gradual (analogue) drop in resistive state followed by a gradual recovery phase regardless of input stimulus polarity, echoing traditional, binary CRS behavior. This analogue switching property opens the possibility of operating the RRAM fuse as a single-component step change detector. Moreover, we discover that the characteristics of the individual RRAM devices used to demonstrate the RRAM fuse concept in this work allow our fuse to be operated in a regime where one of the two constituent devices can be switched largely independently from the other. This property, not present in the traditional CRS, indicates that the inherently analogue RRAM fuse architecture may support additional operational flexibility through, for example, allowing finer control over its resistive state.
Wang J, Serb A, Papavassiliou C, et al., 2021, Analysing and measuring the performance of memristive integrating amplifiers, INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, Vol: 49, Pages: 3507-3525, ISSN: 0098-9886
Leung OM, Schoetz T, Prodromakis T, et al., 2021, Review-Progress in Electrolytes for Rechargeable Aluminium Batteries, JOURNAL OF THE ELECTROCHEMICAL SOCIETY, Vol: 168, ISSN: 0013-4651
Maheshwari S, Serb A, Papavassiliou C, et al., 2021, An Adiabatic Regenerative Capacitive Artificial Neuron, 2021 IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE
Wang J, Serb A, Papavassiliou C, et al., 2021, Accounting for Memristor I-V Non-Linearity in Low Power Memristive Amplifiers, 2021 IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE
Prinzie J, Simanjuntak FM, Leroux P, et al., 2021, Low-power electronic technologies for harsh radiation environments, NATURE ELECTRONICS, Vol: 4, Pages: 243-253, ISSN: 2520-1131
Simanjuntak FM, Chandrasekaran S, Panda D, et al., 2021, Negative effect of cations out-diffusion and auto-doping on switching mechanisms of transparent memristor devices employing ZnO/ITO heterostructure, APPLIED PHYSICS LETTERS, Vol: 118, ISSN: 0003-6951
Stathopoulos S, Tzouvadaki I, Prodromakis T, 2021, Author Correction: UV induced resistive switching in hybrid polymer metal oxide memristors., Sci Rep, Vol: 11
Saleem A, Simanjuntak FM, Chandrasekaran S, et al., 2021, Transformation of digital to analog switching in TaOx-based memristor device for neuromorphic applications, APPLIED PHYSICS LETTERS, Vol: 118, ISSN: 0003-6951
Shen J, Stathopoulos S, Prodromakis T, et al., 2021, A reconfigurable CMOS-memristor active inductor, ISCAS 2020, ISSN: 0271-4310
A methodology is introduced here to exploit the programmability of the memristors in order to realize reconfigurable monolithic analogue circuit elements. Classical network synthesis methods are used to synthesize adjustable active inductors with inductance values exceeding those of on-chip passives by several orders of magnitude. In this paper, a wide range of active inductance values are obtained by employing memristor to control the biasing current of operational transconductance amplifiers used to implement gyrators. The gyration constant of the proposed gyrator will be linearly controlled by memristance state. The implementation of the designed circuit is realized in 0.18µm commercially available complementary metal-oxide-semiconductor (CMOS) technology from TSMC. Circuit performance is simulated using Cadence Virtuoso. The utilized off-chip memristor is a metal-oxide bi-layer memristor which exhibits a non-volatile memristance range of 4.7kΩ to 170kΩ. The active inductance range achieved is from approximately 95µH to 1.55mH with an inductive bandwidth of 69MHz and 18MHz respectively. The total power consumption is between 0.21mW to 1.95mW depending on the memristance and equivalent inductance.
In general, intelligent systems require knowledge databases storing memory associations for mimicking the capabilities of the human brain. Conventional associative memory cells are constructed based on SRAM, a type of volatile memory consisting of large numbers of transistors per stored bit. Here, we present an energy efficient, robust and hardware friendly-associative memory cell design that we designate RC-XNOR-Z. It is based on creating a tuneable RC constant with the help of a modifiable resistance element (RRAM), plus a simplified XNOR gate for generating the output. The overall design has a total component count of 6T1C1R (6 transistors, 1 capacitor, 1 RRAM device), is non-volatile, is designed to work with RRAM devices with very low ON/OFF ratio (≈4), avoids high current DC paths during misses and operates under power supply of 0.95V. Furthermore, we show expected simulated power dissipation per miss including refresh in the order of single-digit nW/bit and power dissipation/hit in the order of 10 µW, which for a clock rate of 1GHz translates into aJ and 100s of pJ dissipation accordingly. This is competitive with state of art DRAM and SRAM.
Stathopoulos S, Tzouvadaki I, Prodromakis T, 2020, UV induced resistive switching in hybrid polymer metal oxide memristors, SCIENTIFIC REPORTS, Vol: 10, ISSN: 2045-2322
Giotis C, Serb A, Stathopoulos S, et al., 2020, Bidirectional Volatile Signatures of Metal-Oxide Memristors-Part I: Characterization, IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol: 67, Pages: 5158-5165, ISSN: 0018-9383
Giotis C, Serb A, Stathopoulos S, et al., 2020, Bidirectional Volatile Signatures of Metal-Oxide Memristors-Part II: Modeling, IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol: 67, Pages: 5166-5173, ISSN: 0018-9383
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