Publications
238 results found
Wang C, Si Z, Jiang X, et al., 2022, Multi-State Memristors and Their Applications: An Overview, IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol: 12, Pages: 723-734, ISSN: 2156-3357
Mifsud A, Shen J, Feng P, et al., 2022, A CMOS-based characterisation platform for emerging RRAM technologies, 2022 IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 75-79
Mass characterisation of emerging memory devices is an essential step in modelling their behaviour for integration within a standard design flow for existing integrated circuit designers. This work develops a novel characterisation platform for emerging resistive devices with a capacity of up to 1 million devices on-chip. Split into four independent sub-arrays, it contains on-chip column-parallel DACs for fast voltage programming of the DUT. On-chip readout circuits with ADCs are also available for fast read operations covering 5-decades of input current (20nA to 2mA). This allows a device’s resistance range to be between 1kΩ and 10MΩ with a minimum voltage range of ±1.5V on the device.
Maheshwari S, Serb A, Papavassiliou C, et al., 2022, An Adiabatic Capacitive Artificial Neuron With RRAM-Based Threshold Detection for Energy-Efficient Neuromorphic Computing, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, Vol: 69, Pages: 3512-3525, ISSN: 1549-8328
Foster P, Huang J, Serb A, et al., 2022, An FPGA-based system for generalised electron devices testing, Scientific Reports, Vol: 12, ISSN: 2045-2322
Electronic systems are becoming more and more ubiquitous as our world digitises. Simultaneously, even basic components are experiencing a wave of improvements with new transistors, memristors, voltage/current references, data converters, etc, being designed every year by hundreds of R &D groups world-wide. To date, the workhorse for testing all these designs has been a suite of lab instruments including oscilloscopes and signal generators, to mention the most popular. However, as components become more complex and pin numbers soar, the need for more parallel and versatile testing tools also becomes more pressing. In this work, we describe and benchmark an FPGA system developed that addresses this need. This general purpose testing system features a 64-channel source-meter unit, and [Formula: see text] banks of 32 digital pins for digital I/O. We demonstrate that this bench-top system can obtain [Formula: see text] current noise floor, [Formula: see text] pulse delivery at [Formula: see text] and [Formula: see text] maximum current drive/channel. We then showcase the instrument's use in performing a selection of three characteristic measurement tasks: (a) current-voltage characterisation of a diode and a transistor, (b) fully parallel read-out of a memristor crossbar array and (c) an integral non-linearity test on a DAC. This work introduces a down-scaled electronics laboratory packaged in a single instrument which provides a shift towards more affordable, reliable, compact and multi-functional instrumentation for emerging electronic technologies.
Yang F, Serb A, Prodromakis T, 2022, Measured behaviour of a memristor-based tuneable instrumentation amplifier, Electronics Letters, Vol: 58, Pages: 570-572, ISSN: 0013-5194
A memristor-based tuneable instrumentation amplifier whose gain value can be adjusted by memristor is implemented and measured. While memristive devices are suitable for implementing reconfigurable circuit designs, their non-linear characteristic and parasitic capacitance can impact performance. In this work, an instrumentation amplifier is built on breadboard using off-the-shelf OpAmps and packaged memristor devices and its performance is assessed. Results are compared with an identical design that preplaces memristors with resistors (losing reconfigurability in the process), to reveal the effects arising from the memristor's characteristics. Effects on frequency response, common mode rejection ratio (CMRR) and total harmonic distortion plus noise (THD+N) are observed. The memristor-based instrumentation amplifier begins to be affected by the non-linearity of the device only when the base OpAmps have a THD value below 0.3%. The bandwidth of the instrumentation amplifier is limited by the parasitic capacitance of memristors, and CMRR has small variation when using memristor to replace the original gain resistor. The THD+N value is large compared with identical design, but it is also found that by applying multiple memristors the increasing of THD+N can be relieved.
Huang J, Stathopoulos S, Serb A, et al., 2022, NeuroPack: An Algorithm-Level Python-Based Simulator for Memristor-Empowered Neuro-Inspired Computing, Frontiers in Nanotechnology, Vol: 4
Emerging two-terminal nanoscale memory devices, known as memristors, have demonstrated great potential for implementing energy-efficient neuro-inspired computing architectures over the past decade. As a result, a wide range of technologies have been developed that, in turn, are described via distinct empirical models. This diversity of technologies requires the establishment of versatile tools that can enable designers to translate memristors’ attributes in novel neuro-inspired topologies. In this study, we present NeuroPack, a modular, algorithm-level Python-based simulation platform that can support studies of memristor neuro-inspired architectures for performing online learning or offline classification. The NeuroPack environment is designed with versatility being central, allowing the user to choose from a variety of neuron models, learning rules, and memristor models. Its hierarchical structure empowers NeuroPack to predict any memristor state changes and the corresponding neural network behavior across a variety of design decisions and user parameter options. The use of NeuroPack is demonstrated herein via an application example of performing handwritten digit classification with the MNIST dataset and an existing empirical model for metal-oxide memristors.
Antoniou G, Yuan P, Koutsokeras L, et al., 2022, Low-power supralinear photocurrent generation via excited state fusion in single-component nanostructured organic photodetectors, JOURNAL OF MATERIALS CHEMISTRY C, Vol: 10, Pages: 7575-7585, ISSN: 2050-7526
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- Citations: 1
Panidi J, Georgiadou DG, Schoetz T, et al., 2022, Advances in Organic and Perovskite Photovoltaics Enabling a Greener Internet of Things, ADVANCED FUNCTIONAL MATERIALS, Vol: 32, ISSN: 1616-301X
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- Citations: 3
Simanjuntak FM, Panidi J, Talbi F, et al., 2022, Formation of a ternary oxide barrier layer and its role in switching characteristic of ZnO-based conductive bridge random access memory devices, APL MATERIALS, Vol: 10, ISSN: 2166-532X
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- Citations: 1
Abbey T, Giotis C, Serb A, et al., 2022, Thermal Effects on Initial Volatile Response and Relaxation Dynamics of Resistive RAM Devices, IEEE ELECTRON DEVICE LETTERS, Vol: 43, Pages: 386-389, ISSN: 0741-3106
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- Citations: 1
Aivali S, Yuan P, Panidi J, et al., 2022, Electron Transporting Perylene Diimide-Based Random Terpolymers with Variable Co-Monomer Feed Ratio: A Route to All-Polymer Based Photodiodes, MACROMOLECULES, Vol: 55, Pages: 672-683, ISSN: 0024-9297
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- Citations: 3
Simanjuntak FM, Talbi F, Kerrigan A, et al., 2022, Electrode Engineering in Memristors Development for Non-/Erasable Storage, Random Number Generator, and Synaptic Applications, Pages: 171-175
We report the process development of ZnO-based memristors and observe various switching phenomena by means of electrode engineering, such as digital-to-analogue transformation, irregular and uniform endurance, and non-erasable switching; we also discuss the potential applications for each of these switching phenomena. The use of inert electrodes induces a high injection of electrons into the switching layer triggering abrupt current changes and, in some cases, resulting in a device breakdown. Meanwhile, a low work function and oxidizable electrode encourage Ohmic contact at the oxide/electrode junction and exhibit gradual switching characteristics. This work addresses the importance of electrode configuration to achieve the desired switching behaviour for specific low-powered electronic applications.
Wang J, Serb A, Wang S, et al., 2022, Hybrid CMOS/Memristor Front-End for Multiunit Activity Processing, Pages: 965-969, ISSN: 0271-4310
Epileptic seizure prediction could help patients stay safe and provide them with opportunities to prevent seizures in advance. This can be realised by a complete system that captures the intracortical neuronal signals from the implantable device, processes the recorded data for discriminating seizures and transfers the information to the personal advisory device. Seizures can be discriminated by monitoring the counts of population spikes and we proposed a spike detection front-end for this application. The proposed discrete-time system amplifies, detects and digitises the spiking with ultra-low power and high precision with the aid of memristor as a trimming device. In this paper, we utilised the measurement methodology for the discrete-time system that combines periodic steady-state analysis and transient simulation to examine its behaviour under sources of uncertainty: noise, process corner and mismatch. The noise performance can be improved by oversampling while maintaining low power consumption. And the memristive devices are capable of compensating the inherent offset and do not induce material impact. Combining work and verification above, the system can be scaled up and/or practical implementation in the next step.
Huang J, Stathopoulos S, Serb A, et al., 2022, A tool for emulating neuromorphic architectures with memristive models and devices, Pages: 1092-1096, ISSN: 0271-4310
Memristors have shown promising features for enhancing neuromorphic computing concepts and AI hardware accelerators. In this paper, we present a user-friendly software infrastructure that allows emulating a wide range of neuromorphic architectures with memristor models. This tool empowers studies that exploit memristors for online learning and online classification tasks, predicting memristor resistive state changes during the training process. The versatility of the tool is showcased through the capability for users to customise parameters in the employed memristor and neuronal models as well as the employed learning rules. This further allows users to validate concepts and their sensitivity across a wide range of parameters. We demonstrate the use of the tool via an MNIST classification task. Finally, we show how this tool can also be used to emulate the concepts under study in-silico with practical memristive devices via appropriate interfacing with commercially available characterisation tools.
Wang J, Serb A, Wang S, et al., 2022, Offset Rejection in a DC-Coupled Hybrid CMOS/Memristor Neural Front-End, Pages: 970-974, ISSN: 0271-4310
One of the challenges of designing neural front-end is to reject the DC offset from electrodes. The conventional AC-coupled solution is to utilise large input capacitors and pseudo-resistors, which have the key limitations of area, linearity and DC drift. In this paper, we propose a DC-coupled solution based on the hybrid CMOS/memristor technique. The spike detection is realised by thresholding in the proposed front-end, which consists of a memristive amplifier and a DLC. The amplifier boosts micro-volt neural signals to milli-volt through integration, making it recognised by the DLC. In addition, the memristor is utilised as a trimming device along the current branch for the purpose of tuning the offset voltage. It is capable of compensating up to 50mV DC offset. With the oversampling ratio reaching 95, the accuracy spike detection can be maintained to 95% and the frontend consumes 123.5nW in our design example. The proposed DC offset front-end is capable of reaching high accuracy and low power consumption.
Simanjuntak FM, Hsu C-L, Abbey T, et al., 2021, Conduction channel configuration controlled digital and analog response in TiO2-based inorganic memristive artificial synapses, APL MATERIALS, Vol: 9, ISSN: 2166-532X
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- Citations: 1
Lanza M, Waser R, Ielmini D, et al., 2021, Standards for the Characterization of Endurance in Resistive Switching Devices., ACS Nano, Vol: 15, Pages: 17214-17231
Resistive switching (RS) devices are emerging electronic components that could have applications in multiple types of integrated circuits, including electronic memories, true random number generators, radiofrequency switches, neuromorphic vision sensors, and artificial neural networks. The main factor hindering the massive employment of RS devices in commercial circuits is related to variability and reliability issues, which are usually evaluated through switching endurance tests. However, we note that most studies that claimed high endurances >106 cycles were based on resistance versus cycle plots that contain very few data points (in many cases even <20), and which are collected in only one device. We recommend not to use such a characterization method because it is highly inaccurate and unreliable (i.e., it cannot reliably demonstrate that the device effectively switches in every cycle and it ignores cycle-to-cycle and device-to-device variability). This has created a blurry vision of the real performance of RS devices and in many cases has exaggerated their potential. This article proposes and describes a method for the correct characterization of switching endurance in RS devices; this method aims to construct endurance plots showing one data point per cycle and resistive state and combine data from multiple devices. Adopting this recommended method should result in more reliable literature in the field of RS technologies, which should accelerate their integration in commercial products.
Maheshwari S, Stathopoulos S, Wang J, et al., 2021, Design flow for hybrid CMOS/memristor systems--Part I: modeling and verification steps, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol: 68, Pages: 4862-4875, ISSN: 1549-8328
Memristive technology has experienced explosive growth in the last decade, with multiple device structures being developed for a wide range of applications. However, transitioning the technology from the lab into the marketplace requires the development of an accessible and user-friendly design flow, supported by an industry-grade toolchain. In this work, we demonstrate the behaviour of our in-house fabricated custom memristor model and its integration into the Cadence Electronic Design Automation (EDA) tools for verification. Various input stimuli were given to record the memristive device characteristics both at the device level as well as the schematic level for verification of the memristor model. This design flow from device to industrial level EDA tools is the first step before the model can be used and integrated with Complementary Metal-Oxide Semiconductor (CMOS) in applications for hybrid memristor/CMOS system design.
Maheshwari S, Stathopoulos S, Wang J, et al., 2021, Design flow for hybrid CMOS/memristor systems--Part II: circuit schematics and layout, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol: 68, Pages: 4876-4888, ISSN: 1549-8328
\normalsize The capability of in-memory computation, reconfigurability, low power operation as well as multistate operation of the memristive device deems them a suitable candidate for designing electronic circuits with a broad range of applications. Besides, the integrability of memristor with CMOS enables it to use in logic circuits too. In this work, we demonstrate with examples the design flow for memristor-based electronics, after the custom memristor model already being integrated and validated into our chosen Computer-Aided Design (CAD) tool to performing layout-versus-schematic and post-layout checks including the memristive device. We envisage that this step-by-step guide to introducing memristor into the standard integrated circuit design flow will be a useful reference document for both device developers who wish to benchmark their technologies and circuit designers who wish to experiment with memristive-enhanced systems.
Manouras V, Stathopoulos S, Serb A, et al., 2021, Technology agnostic frequency characterization methodology for memristors, SCIENTIFIC REPORTS, Vol: 11, ISSN: 2045-2322
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- Citations: 4
Vaidya D, Kothari S, Abbey T, et al., 2021, Compact Modeling of the Switching Dynamics and Temperature Dependencies in TiOx Memristors-Part II: Physics-Based Model, IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol: 68, Pages: 4885-4890, ISSN: 0018-9383
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- Citations: 1
Vaidya D, Kothari S, Abbey T, et al., 2021, Compact Modeling of the Switching Dynamics and Temperature Dependencies in TiOx-Based Memristors - Part I: Behavioral Model, IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol: 68, Pages: 4877-4884, ISSN: 0018-9383
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- Citations: 3
Serb A, Khiat A, Prodromakis T, 2021, Practical demonstration of a RRAM memory fuse, International Journal of Circuit Theory and Applications, Vol: 49, Pages: 2363-2372, ISSN: 0098-9886
Since its inception, the resistive random access memory (RRAM) fuse has been a good example of how small numbers of RRAM devices can be combined to obtain useful behaviors unachievable by individual devices. In this work, we link the RRAM fuse concept with that of the complementary resistive switch (CRS), exploit that link to experimentally demonstrate a practical RRAM fuse using TiOx-based RRAM cells, and explain its basic operational principles. The fuse is stimulated by trains of identical pulses where successive pulse trains feature opposite polarities. In response, we observe a gradual (analogue) drop in resistive state followed by a gradual recovery phase regardless of input stimulus polarity, echoing traditional, binary CRS behavior. This analogue switching property opens the possibility of operating the RRAM fuse as a single-component step change detector. Moreover, we discover that the characteristics of the individual RRAM devices used to demonstrate the RRAM fuse concept in this work allow our fuse to be operated in a regime where one of the two constituent devices can be switched largely independently from the other. This property, not present in the traditional CRS, indicates that the inherently analogue RRAM fuse architecture may support additional operational flexibility through, for example, allowing finer control over its resistive state.
Wang J, Serb A, Papavassiliou C, et al., 2021, Analysing and measuring the performance of memristive integrating amplifiers, INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, Vol: 49, Pages: 3507-3525, ISSN: 0098-9886
Manouras V, Stathopoulos S, Garlapati SK, et al., 2021, Frequency Response of Metal-Oxide Memristors, IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol: 68, Pages: 3636-3642, ISSN: 0018-9383
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- Citations: 5
Leung OM, Schoetz T, Prodromakis T, et al., 2021, Review-Progress in Electrolytes for Rechargeable Aluminium Batteries, JOURNAL OF THE ELECTROCHEMICAL SOCIETY, Vol: 168, ISSN: 0013-4651
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- Citations: 12
Maheshwari S, Serb A, Papavassiliou C, et al., 2021, An Adiabatic Regenerative Capacitive Artificial Neuron, 2021 IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE
Wang J, Serb A, Papavassiliou C, et al., 2021, Accounting for Memristor I-V Non-Linearity in Low Power Memristive Amplifiers, 2021 IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE
Prinzie J, Simanjuntak FM, Leroux P, et al., 2021, Low-power electronic technologies for harsh radiation environments, NATURE ELECTRONICS, Vol: 4, Pages: 243-253, ISSN: 2520-1131
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- Citations: 12
Simanjuntak FM, Chandrasekaran S, Panda D, et al., 2021, Negative effect of cations out-diffusion and auto-doping on switching mechanisms of transparent memristor devices employing ZnO/ITO heterostructure, APPLIED PHYSICS LETTERS, Vol: 118, ISSN: 0003-6951
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- Citations: 3
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