259 results found
Si Z, Wang C, Jiang X, et al., 2023, Memristor-Assisted Background Calibration for SAR ADCs: A Feasibility Study, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol: 70, Pages: 3497-3508, ISSN: 1549-8328
This paper proposes a memristor-assisted sign-based background calibration scheme for analog-to-digital converters (ADCs). The scheme was implemented and validated in a 12-bit asynchronous successive approximation register (SAR) ADC, which consists of a hybrid binary weighted/R-2R digital-to-analog converter (binary/R-2R DAC) and other peripheral circuits. This hybrid DAC, in which one redundancy bit is introduced, is built with a memristor and standard polysilicon resistors. The proposed calibration technique can detect the errors caused by DAC mismatches and correct them by adjusting the resistance of the memristor (memristance) in a feedback loop. The implemented circuit takes the memristor's advantages such as small area and resistance switching property. The proposed scheme has been designed and simulated in a standard 180 nm CMOS process. Eventually, a monolithic CMOS/memristor chip will be fabricated with the CMOS part processed at a standard foundry and the memristors integrated through post-CMOS processing in house. Simulation results demonstrate the feasibility of exploiting memristors to improve the linearity of high-resolution SAR ADCs. The designed calibration scheme can effectively reduce the integral non-linearity (INL) and differential non-linearity (DNL) of the 12-bit SAR ADC.
Tzouvadaki I, Gkoupidenis P, Vassanelli S, et al., 2023, Interfacing Biology and Electronics with Memristive Materials., Adv Mater, Vol: 35
Memristive technologies promise to have a large impact on modern electronics, particularly in the areas of reconfigurable computing and artificial intelligence (AI) hardware. Meanwhile, the evolution of memristive materials alongside the technological progress is opening application perspectives also in the biomedical field, particularly for implantable and lab-on-a-chip devices where advanced sensing technologies generate a large amount of data. Memristive devices are emerging as bioelectronic links merging biosensing with computation, acting as physical processors of analog signals or in the framework of advanced digital computing architectures. Recent developments in the processing of electrical neural signals, as well as on transduction and processing of chemical biomarkers of neural and endocrine functions, are reviewed. It is concluded with a critical perspective on the future applicability of memristive devices as pivotal building blocks in bio-AI fusion concepts and bionic schemes.
Prodromakis T, Papavassiliou C, Si Z, et al., 2023, An improved data-driven memristor model accounting for sequences stimulus features, 2023 IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, ISSN: 2158-1525
The natural similarity between the emerging memristive technology and synapses makes memristor a promising device in the spiking input based neuromorphic systems. However, while asynchronous signal processing relies on memristor's response under the pulses stimulus, hardly any memristor models take the impact of sequences features on device behaviour into account. This paper proposes an optimized data-driven compact memristor model where the boundary of its internal state variable-resistive state (RS) is modelled with pulse amplitude and pulse width based on characterisation data. The model has been developed in Verilog-A and verified in Cadence Virtuoso Electronic Design Automation (EDA) tools. Based on the simulation, we further introduce a new concept “Effective Time Window”. Along with the observed pulse width modulated resistance, more potential circuit applications can be implemented based on a more realistic memristor switching behaviour.
Aitchison C, Halak B, Serb A, et al., 2023, A memristor fingerprinting and characterisation methodology for hardware security., Sci Rep, Vol: 13
The modern IC supply chain encompasses a large number of steps and manufacturers. In many applications it is critically important that chips are of the right quality and are assured to have been obtained from the legitimate supply chain. To this end, it is necessary to be able to uniquely identify systems to aid in supply chain tracking and quality assurance. Many identifiers, however, can be cloned onto counterfeit devices and are therefore untrustworthy. This paper proposes a methodology for using post-CMOS memristor devices as a fingerprint to uniquely identify ICs. To achieve this, memristors' unique and variable I-V characteristics are exploited to produce a fingerprint that can be generally applicable to a wide variety of different memristor technologies and identifiable over time, even where cell retention is non-ideal. In doing so it aims to minimise the hardware required on-chip both to minimise cost and maximise the auditability of the system. The methodology is applied to a [Formula: see text] memristor technology, and shown to be able to identify cells in a set.
Panca A, Panidi J, Faber H, et al., 2023, Flexible Oxide Thin Film Transistors, Memristors, and Their Integration, Advanced Functional Materials, Vol: 33, ISSN: 1616-301X
Flexible electronics have seen extensive research over the past years due to their potential stretchability and adaptability to non-flat surfaces. They are key to realizing low-power sensors and circuits for wearable electronics and Internet of Things (IoT) applications. Semiconducting metal-oxides are a prime candidate for implementing flexible electronics as their conformal deposition methods lend themselves to the idiosyncrasies of non-rigid substrates. They are also a major component for the development of resistive memories (memristors) and as such their monolithic integration with thin film electronics has the potential to lead to novel all-metal-oxide devices combining memory and computing on a single node. This review focuses on exploring the recent advances across all these fronts starting from types of suitable substrates and their mechanical properties, different types of fabrication methods for thin film transistors and memristors applicable to flexible substrates (vacuum- or solution-based), applications and comparison with rigid substrates while additionally delving into matters associated with their monolithic integration.
Huang J, Serb A, Stathopoulos S, et al., 2023, Text classification in memristor-based spiking neural networks, Neuromorphic Computing and Engineering, Vol: 3
Memristors, emerging non-volatile memory devices, have shown promising potential in neuromorphic hardware designs, especially in spiking neural network (SNN) hardware implementation. Memristor-based SNNs have been successfully applied in a wide range of applications, including image classification and pattern recognition. However, implementing memristor-based SNNs in text classification is still under exploration. One of the main reasons is that training memristor-based SNNs for text classification is costly due to the lack of efficient learning rules and memristor non-idealities. To address these issues and accelerate the research of exploring memristor-based SNNs in text classification applications, we develop a simulation framework with a virtual memristor array using an empirical memristor model. We use this framework to demonstrate a sentiment analysis task in the IMDB movie reviews dataset. We take two approaches to obtain trained SNNs with memristor models: (1) by converting a pre-trained artificial neural network (ANN) to a memristor-based SNN, or (2) by training a memristor-based SNN directly. These two approaches can be applied in two scenarios: offline classification and online training. We achieve the classification accuracy of 85.88% by converting a pre-trained ANN to a memristor-based SNN and 84.86% by training the memristor-based SNN directly, given that the baseline training accuracy of the equivalent ANN is 86.02%. We conclude that it is possible to achieve similar classification accuracy in simulation from ANNs to SNNs and from non-memristive synapses to data-driven memristive synapses. We also investigate how global parameters such as spike train length, the read noise, and the weight updating stop conditions affect the neural networks in both approaches. This investigation further indicates that the simulation using statistic memristor models in the two approaches presented by this paper can assist the exploration of memristor-based SNNs in natur
As autonomous devices are increasingly used in security and safety-critical applications the security of the systems they comprise is of increasing concern. In such situations it is important that devices can be securely identified and trusted. When an IC or device is in the supply chain, or in the field, the lack of control over actors who can obtain physical access can compromise the trust and overall security of a system. Counterfeit chips may be incorporated into the device, compromising reliability or security. Additionally, for implemented devices, keys stored on-device may be copied by a bad actor. To help improve the security of such devices this paper proposes a new physical unclonable function (PUF) architecture, based on a TiOx memristor-based resistive memory (RRAM), that exploits the inherent analogue non-linearity in resistance of some memristor technologies. By directly exploiting non-linearity of memristor cells, rather than relying on the devices' absolute resistance at a single test voltage, a multi-bit-per-comparison PUF is created. As the architecture directly exploits cells' non-linearity, an additional source of hard-to-clone entropy is incorporated.
Jiang X, Sbandati C, Reynolds G, et al., 2023, A Neural Recording System with 16 Reconfigurable Front-end Channels and Memristive Processing/Memory Unit
This paper proposes a neural recording system that supports recording of action potentials (APs), local field potentials (LFPs), or full-band neural signals (APs plus LFPs) by exploiting 16 reconfigurable front-end channels. To store and process the recorded signals, an off-chip 1 transistor 1 memristor (ITIR) crossbar array with optimized row/column selection logic is employed. The crossbar array is divided into four allocatable memory zones. The front-end channels are designed to filter the input signals to the bands of interest with a programmable gain of 100x or 1000x. Each front-end channel comprises an AC-coupled low-noise amplifier (LNA) which has an inherent high-pass filter (HPF), a passive first-order low-pass filter (LPF), and a variable gain amplifier (VGA). The VGA also acts as a butter to interface with the memristor array. A reconfigurable pseudo-resistor is used to set variable high-pass corner frequencies for different recording modes. The total input-referred integrated noise of the entire channel is less than 5.6µ V_rms in the AP band (500- 10kHz) and less than 4.55µ V_rms in the LFP band (1-500Hz). Implemented in a standard 180nm CMOS process, each channel occupies 0.035 mm^2 chip area and consumes 20.4µW with a 1. 8V power supply. The memristor array is post-processed on the CMOS back-end-of-line (BEOL) in-house, which will be used to process and encode the channel outputs into memristive states.
Agwa S, Prodromakis T, 2023, Bent-Pyramid: Towards A Quasi-Stochastic Data Representation for AI Hardware
The applications of the Artificial Intelligence have been increasingly used with huge datasets for many purposes. The beyond Von Neumann architectures (like digital and analog in-memory computing) are proposed to mitigate the data-movement bottleneck. However, they are struggling with the limitations of the conventional data representations: either the computation complexity of the digital binary domain or the interfacing and scalability issues of the analog domain; Meanwhile, the stochastic computing domain suffers from the generation complexity bottleneck which degrades the benefits of its computation simplicity. This paper presents a new Bent-Pyramid system which acts as a quasi-stochastic data representation. The new Bent-Pyramid system utilizes two complementary fixed sets of bitstreams to perform deterministic multiplication. The Bent-Pyramid inherits the same multiplication simplicity of the stochastic computing while avoiding the stochastic number generation complexity. The Vector-Matrix Multiplication benchmarking shows that the 10bit Bent-Pyramid system has a comparable accuracy to the 16bit stochastic computing. The generation circuit of the 10-bit Bent-Pyramid reduces the energy and the latency of the 16-bit stochastic counterpart by 15.15x and 16.0x respectively.
Agwa S, Papandroulidakis G, Prodromakis T, 2023, A 1T1R+2T Analog Content-Addressable Memory Pixel for Online Template Matching, ISSN: 0271-4310
The template matching approach has a promising momentum to build energy-efficient edge classifiers for var-ious implantable and wearable medical devices. To mitigate the analog/digital cross-domain interfacing complexity, analog content-addressable memories can be used efficiently to form the back-end classifiers by receiving the analog inputs and generating the digital classification outputs. This paper presents a novel memristor-based analog content-addressable memory pixel 1TIR+2T with 2.0x smaller footprint than its counterparts in the literature. The new compact pixel utilizes only one RRAM device through a 1T1R voltage divider circuit while exploiting the complementary behavior of the nMOS and pMOS transistors to determine the lower and upper bounds of the matching voltage range. The simulation results show that the 1T1R+2T pixel has a promising tunability with matching windows range from 50 mV to 200 mV according to the RRAM resistance value of the 1T1R voltage divider.
Agwa S, Prodromakis T, 2023, Digital in-memory stochastic computing architecture for vector-matrix multiplication, Frontiers in Nanotechnology, Vol: 5
The applications of the Artificial Intelligence are currently dominating the technology landscape. Meanwhile, the conventional Von Neumann architectures are struggling with the data-movement bottleneck to meet the ever-increasing performance demands of these data-centric applications. Moreover, The vector-matrix multiplication cost, in the binary domain, is a major computational bottleneck for these applications. This paper introduces a novel digital in-memory stochastic computing architecture that leverages the simplicity of the stochastic computing for in-memory vector-matrix multiplication. The proposed architecture incorporates several new approaches including a new stochastic number generator with ideal binary-to-stochastic mapping, a best seeding approach for accurate-enough low stochastic bit-precisions, a hybrid stochastic-binary accumulation approach for vector-matrix multiplication, and the conversion of conventional memory read operations into on-the-fly stochastic multiplication operations with negligible overhead. Thanks to the combination of these approaches, the accuracy analysis of the vector-matrix multiplication benchmark shows that scaling down the stochastic bit-precision from 16-bit to 4-bit achieves nearly the same average error (less than 3%). The derived analytical model of the proposed in-memory stochastic computing architecture demonstrates that the 4-bit stochastic architecture achieves the highest throughput per sub-array (122 Ops/Cycle), which is better than the 16-bit stochastic precision by 4.36x, while still maintaining a small average error of 2.25%.
Tzouvadaki I, Prodromakis T, 2023, Large-scale nano-biosensing technologies, Frontiers in Nanotechnology, Vol: 5
Nanoscale technologies have brought significant advancements to modern diagnostics, enabling unprecedented bio-chemical sensitivities that are key to disease monitoring. At the same time, miniaturized biosensors and their integration across large areas enabled tessellating these into high-density biosensing panels, a key capability for the development of high throughput monitoring: multiple patients as well as multiple analytes per patient. This review provides a critical overview of various nanoscale biosensing technologies and their ability to unlock high testing throughput without compromising detection resilience. We report on the challenges and opportunities each technology presents along this direction and present a detailed analysis on the prospects of both commercially available and emerging biosensing technologies.
Panca AG, Serb A, Stathopoulos S, et al., 2023, Automated RRAM measurements using a semi-Automated probe station and ArC ONE interface
Resistive Random Access Technology (RRAM) is quickly reaching industrial maturity. A key element towards achieving lasting commercial success, however, is automated testing; useful for performance benchmarking and rapid prototyping of new flavours of technology. Here we present a wafer-scale semi-Automated RRAM device testing platform.
In this work, we present the design of a dynamic latched comparator showing tuneability using the RRAM devices in the source terminal of the input nMOS transistors in 180nm CMOS technology. The memristor-based design has been compared with the conventional design (without RRAM) based on dynamic offset in the presence of mismatch, accuracy with noise, settling time and power consumption across process, voltage and temperature (PVT) variations. The RRAM-based design demonstrates a wide range of dynamic offset spanning from - 345mV to +V_DD/2 (no crossover detected). The noise simulation results in a shift of -122µ V compared to the conventional design which can be compensated using the RRAM devices. For different resistive states and PVT variations, a wide range of power dissipation was seen. For unbalanced resistive states, the power consumption is \approx7% at FF', \approx2.5% at 'TT' and \approx0.5% at 'SS' less in comparison to the conventional design. It can be seen that the RRAM-based dynamic comparator has significantly established a wide range of tuneability, can compensate for changes arising due to process and mismatches and increase accuracy and reliability in comparison to the conventional design.
Wang C, Si Z, Jiang X, et al., 2022, Multi-State Memristors and Their Applications: An Overview, IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol: 12, Pages: 723-734, ISSN: 2156-3357
Mifsud A, Shen J, Feng P, et al., 2022, A CMOS-based characterisation platform for emerging RRAM technologies, 2022 IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 75-79
Mass characterisation of emerging memory devices is an essential step in modelling their behaviour for integration within a standard design flow for existing integrated circuit designers. This work develops a novel characterisation platform for emerging resistive devices with a capacity of up to 1 million devices on-chip. Split into four independent sub-arrays, it contains on-chip column-parallel DACs for fast voltage programming of the DUT. On-chip readout circuits with ADCs are also available for fast read operations covering 5-decades of input current (20nA to 2mA). This allows a device’s resistance range to be between 1kΩ and 10MΩ with a minimum voltage range of ±1.5V on the device.
Founta E, Schoetz T, Georgiadou DG, et al., 2022, Nanocellulose-Based Flexible Electrodes for Safe and Sustainable Energy Storage, ECS Meeting Abstracts, Vol: MA2022-02, Pages: 275-275
<jats:p> The intensive use of battery-powered electronic devices, in addition to the challenging recycling requirements, have contributed to the accumulation of e-waste, one of the most alarming environmental issues of the modern world. This urges the importance of developing advanced energy storage systems by using non-toxic and more sustainable materials<jats:sup>1</jats:sup>. Nanocellulose as the most abundant bio-polymer, can tackle current ecological and safety concerns but also keep up with contemporary resilience requisites in powering flexible electronics. Herein, we present the development of organic nanocellulose-based battery electrodes, that can be used in applications with relatively low energy storage demands, such as medical systems, wearables and bendable Internet of Things (IoT) devices. We investigate hybrid electrodes composed of nanocellulose fibres and carbon-based battery active materials, by implementing a safer, aqueous fabrication processing and with a focus on understanding the underlying charge storage mechanisms<jats:sup>2</jats:sup>. The main constituent of the electrodes is a porous nanocellulose network that maintains structural integrity acting as a binder but also transports ions from an organic electrolyte to the active battery material with reduced diffusion limitations. The overall battery structure is flexible and mechanically robust, minimizing any volume changes during charge/discharge, which translates to cycling stability<jats:sup>3</jats:sup>.</jats:p> <jats:p>The nanocellulose-based electrodes were manufactured by using different techniques including vacuum filtration and blade coating, and yielded free-standing and current-collector-integrated electrodes. Structural properties and surface morphology were examined via atomic force microscopy (tapping mode and conductive-AFM), and scanning electron microscopy with energy dispersive X-ray spectroscopy (SEM-
Maheshwari S, Serb A, Papavassiliou C, et al., 2022, An Adiabatic Capacitive Artificial Neuron With RRAM-Based Threshold Detection for Energy-Efficient Neuromorphic Computing, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, Vol: 69, Pages: 3512-3525, ISSN: 1549-8328
Foster P, Huang J, Serb A, et al., 2022, An FPGA-based system for generalised electron devices testing, Scientific Reports, Vol: 12, ISSN: 2045-2322
Electronic systems are becoming more and more ubiquitous as our world digitises. Simultaneously, even basic components are experiencing a wave of improvements with new transistors, memristors, voltage/current references, data converters, etc, being designed every year by hundreds of R &D groups world-wide. To date, the workhorse for testing all these designs has been a suite of lab instruments including oscilloscopes and signal generators, to mention the most popular. However, as components become more complex and pin numbers soar, the need for more parallel and versatile testing tools also becomes more pressing. In this work, we describe and benchmark an FPGA system developed that addresses this need. This general purpose testing system features a 64-channel source-meter unit, and [Formula: see text] banks of 32 digital pins for digital I/O. We demonstrate that this bench-top system can obtain [Formula: see text] current noise floor, [Formula: see text] pulse delivery at [Formula: see text] and [Formula: see text] maximum current drive/channel. We then showcase the instrument's use in performing a selection of three characteristic measurement tasks: (a) current-voltage characterisation of a diode and a transistor, (b) fully parallel read-out of a memristor crossbar array and (c) an integral non-linearity test on a DAC. This work introduces a down-scaled electronics laboratory packaged in a single instrument which provides a shift towards more affordable, reliable, compact and multi-functional instrumentation for emerging electronic technologies.
Yang F, Serb A, Prodromakis T, 2022, Measured behaviour of a memristor-based tuneable instrumentation amplifier, Electronics Letters, Vol: 58, Pages: 570-572, ISSN: 0013-5194
A memristor-based tuneable instrumentation amplifier whose gain value can be adjusted by memristor is implemented and measured. While memristive devices are suitable for implementing reconfigurable circuit designs, their non-linear characteristic and parasitic capacitance can impact performance. In this work, an instrumentation amplifier is built on breadboard using off-the-shelf OpAmps and packaged memristor devices and its performance is assessed. Results are compared with an identical design that preplaces memristors with resistors (losing reconfigurability in the process), to reveal the effects arising from the memristor's characteristics. Effects on frequency response, common mode rejection ratio (CMRR) and total harmonic distortion plus noise (THD+N) are observed. The memristor-based instrumentation amplifier begins to be affected by the non-linearity of the device only when the base OpAmps have a THD value below 0.3%. The bandwidth of the instrumentation amplifier is limited by the parasitic capacitance of memristors, and CMRR has small variation when using memristor to replace the original gain resistor. The THD+N value is large compared with identical design, but it is also found that by applying multiple memristors the increasing of THD+N can be relieved.
Giotis C, Serb A, Manouras V, et al., 2022, Palimpsest memories stored in memristive synapses., Sci Adv, Vol: 8
Biological synapses store multiple memories on top of each other in a palimpsest fashion and at different time scales. Palimpsest consolidation is facilitated by the interaction of hidden biochemical processes governing synaptic efficacy during varying lifetimes. This arrangement allows idle memories to be temporarily overwritten without being forgotten, while previously unseen memories are used in the short term. While embedded artificial intelligence can greatly benefit from this functionality, a practical demonstration in hardware is missing. Here, we show how the intrinsic properties of metal-oxide volatile memristors emulate the processes supporting biological palimpsest consolidation. Our memristive synapses exhibit an expanded doubled capacity and protect a consolidated memory while up to hundreds of uncorrelated short-term memories temporarily overwrite it, without requiring specialized instructions. We further demonstrate this technology in the context of visual working memory. This showcases how emerging memory technologies can efficiently expand the capabilities of artificial intelligence hardware toward more generalized learning memories.
Manouras V, Stathopoulos S, Serb A, et al., 2022, Selectively biased tri-terminal vertically-integrated memristor configuration., Sci Rep, Vol: 12
Memristors, when utilized as electronic components in circuits, can offer opportunities for the implementation of novel reconfigurable electronics. While they have been used in large arrays, studies in ensembles of devices are comparatively limited. Here we propose a vertically stacked memristor configuration with a shared middle electrode. We study the compound resistive states presented by the combined in-series devices and we alter them either by controlling each device separately, or by altering the full configuration, which depends on selective usage of the middle floating electrode. The shared middle electrode enables a rare look into the combined system, which is not normally available in vertically stacked devices. In the course of this study, it was found that separate switching of individual devices carries over its effects to the Complete device (albeit non-linearly), enabling increased resistive state range, which leads to a larger number of distinguishable states (above SNR variance limits) and hence enhanced device memory. Additionally, by applying a switching stimulus to the external electrodes it is possible to switch both devices simultaneously, making the entire configuration a voltage divider with individual memristive components. Through usage of this type of configuration and by taking advantage of the voltage division, it is possible to surge-protect fragile devices, while it was also found that simultaneous reset of stacked devices is possible, significantly reducing the required reset time in larger arrays.
Huang J, Stathopoulos S, Serb A, et al., 2022, NeuroPack: An Algorithm-Level Python-Based Simulator for Memristor-Empowered Neuro-Inspired Computing, Frontiers in Nanotechnology, Vol: 4
Emerging two-terminal nanoscale memory devices, known as memristors, have demonstrated great potential for implementing energy-efficient neuro-inspired computing architectures over the past decade. As a result, a wide range of technologies have been developed that, in turn, are described via distinct empirical models. This diversity of technologies requires the establishment of versatile tools that can enable designers to translate memristors’ attributes in novel neuro-inspired topologies. In this study, we present NeuroPack, a modular, algorithm-level Python-based simulation platform that can support studies of memristor neuro-inspired architectures for performing online learning or offline classification. The NeuroPack environment is designed with versatility being central, allowing the user to choose from a variety of neuron models, learning rules, and memristor models. Its hierarchical structure empowers NeuroPack to predict any memristor state changes and the corresponding neural network behavior across a variety of design decisions and user parameter options. The use of NeuroPack is demonstrated herein via an application example of performing handwritten digit classification with the MNIST dataset and an existing empirical model for metal-oxide memristors.
Antoniou G, Yuan P, Koutsokeras L, et al., 2022, Low-power supralinear photocurrent generation via excited state fusion in single-component nanostructured organic photodetectors, JOURNAL OF MATERIALS CHEMISTRY C, Vol: 10, Pages: 7575-7585, ISSN: 2050-7526
Panidi J, Georgiadou DG, Schoetz T, et al., 2022, Advances in Organic and Perovskite Photovoltaics Enabling a Greener Internet of Things, ADVANCED FUNCTIONAL MATERIALS, Vol: 32, ISSN: 1616-301X
Simanjuntak FM, Panidi J, Talbi F, et al., 2022, Formation of a ternary oxide barrier layer and its role in switching characteristic of ZnO-based conductive bridge random access memory devices, APL MATERIALS, Vol: 10, ISSN: 2166-532X
Abbey T, Giotis C, Serb A, et al., 2022, Thermal Effects on Initial Volatile Response and Relaxation Dynamics of Resistive RAM Devices, IEEE ELECTRON DEVICE LETTERS, Vol: 43, Pages: 386-389, ISSN: 0741-3106
Aivali S, Yuan P, Panidi J, et al., 2022, Electron Transporting Perylene Diimide-Based Random Terpolymers with Variable Co-Monomer Feed Ratio: A Route to All-Polymer Based Photodiodes, MACROMOLECULES, Vol: 55, Pages: 672-683, ISSN: 0024-9297
Wang J, Serb A, Wang S, et al., 2022, Offset Rejection in a DC-Coupled Hybrid CMOS/Memristor Neural Front-End, Pages: 970-974, ISSN: 0271-4310
One of the challenges of designing neural front-end is to reject the DC offset from electrodes. The conventional AC-coupled solution is to utilise large input capacitors and pseudo-resistors, which have the key limitations of area, linearity and DC drift. In this paper, we propose a DC-coupled solution based on the hybrid CMOS/memristor technique. The spike detection is realised by thresholding in the proposed front-end, which consists of a memristive amplifier and a DLC. The amplifier boosts micro-volt neural signals to milli-volt through integration, making it recognised by the DLC. In addition, the memristor is utilised as a trimming device along the current branch for the purpose of tuning the offset voltage. It is capable of compensating up to 50mV DC offset. With the oversampling ratio reaching 95, the accuracy spike detection can be maintained to 95% and the frontend consumes 123.5nW in our design example. The proposed DC offset front-end is capable of reaching high accuracy and low power consumption.
This data is extracted from the Web of Science and reproduced under a licence from Thomson Reuters. You may not copy or re-distribute this data in whole or in part without the written consent of the Science business of Thomson Reuters.