Imperial College London
Professor Wayne Luk

ProfessorWayneLuk

Faculty of Engineering, Department of Computing

Professor of Computer Engineering
 
 
 
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Contact

 

+44 (0)20 7594 8313w.luk Website

 
 
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Location

 

434Huxley BuildingSouth Kensington Campus

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Summary

 

Publications

Citation

BibTex format

@inproceedings{Zhao:2018:10.1109/ASAP.2018.8445088,
author = {Zhao, R and Liu, S and Ng, H and Wang, E and Davis, JJ and Niu, X and Wang, X and Shi, H and Constantinides, G and Cheung, P and Luk, W},
doi = {10.1109/ASAP.2018.8445088},
pages = {1--8},
publisher = {IEEE},
title = {Hardware Compilation of Deep Neural Networks: An Overview (invited)},
url = {http://dx.doi.org/10.1109/ASAP.2018.8445088},
year = {2018}
}
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RIS format (EndNote, RefMan)

TY  - CPAPER
AB  - Deploying a deep neural network model on a reconfigurable platform, such as an FPGA, is challenging due to the enormous design spaces of both network models and hardware design. A neural network model has various layer types, connection patterns and data representations, and the corresponding implementation can be customised with different architectural and modular parameters. Rather than manually exploring this design space, it is more effective to automate optimisation throughout an end-to-end compilation process. This paper provides an overview of recent literature proposing novel approaches to achieve this aim. We organise materials to mirror a typical compilation flow: front end, platform-independent optimisation and back end. Design templates for neural network accelerators are studied with a specific focus on their derivation methodologies. We also review previous work on network compilation and optimisation for other hardware platforms to gain inspiration regarding FPGA implementation. Finally, we propose some future directions for related research.
AU  - Zhao,R
AU  - Liu,S
AU  - Ng,H
AU  - Wang,E
AU  - Davis,JJ
AU  - Niu,X
AU  - Wang,X
AU  - Shi,H
AU  - Constantinides,G
AU  - Cheung,P
AU  - Luk,W
DO  - 10.1109/ASAP.2018.8445088
EP  - 8
PB  - IEEE
PY  - 2018///
SP  - 1
TI  - Hardware Compilation of Deep Neural Networks: An Overview (invited)
UR  - http://dx.doi.org/10.1109/ASAP.2018.8445088
UR  - https://ieeexplore.ieee.org/document/8445088/
UR  - http://hdl.handle.net/10044/1/62208
ER  -
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