Publications
45 results found
Huang J, Wang C, Zhou T, et al., 2023, A Shifting Current Mirror Driver Circuit for Electrical Impedance Tomography Applications, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol: 70, Pages: 3832-3836, ISSN: 1549-7747
This brief describes a high power efficiency, high linearity current driver for wearable electrical impedance tomography (EIT). It is extremely important to improve the power efficiency of the current driver circuit for wearable EIT applications because it consumes the majority of the power. As such, we propose a multi-stage shifting current mirror (S-CM) current-steering current driver circuit with customized dynamic element matching (DEM) techniques to suppress harmonic distortion (HD) to the greatest extent. Furthermore, the placement of switches in the current mirror circuit is optimized to reduce glitches during the switching phases. Operating between 14 MHz to 56 MHz, the power consumptions for the current mirror and the digital control logic are 21.6-141.6 μ W and 64.8-438 μ W, respectively. The proposed circuit has demonstrated an excellent energy efficiency of 0.3 μ W/kHz while maintaining a total harmonic distortion (HD) of <-43 dB (0.7%).
Tan G, Qin X, Liu Y, et al., 2023, A 10MHz-BW 85dB-DR CT 0-4 MASH Delta-Sigma Modulator Achieving plus dBFS MSA, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, ISSN: 1549-8328
Hu Y, Liu Y, Qin X, et al., 2023, A Two-Channel Time-Interleaved Continuous-Time Third-Order CIFF-Based Delta-Sigma Modulator, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, ISSN: 1549-8328
Chen K, Wang B, Liu Y, et al., 2023, A Two-Phase Multi-Bit Incremental ADC With Variable Loop Order, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, Vol: 70, Pages: 2724-2728, ISSN: 1549-7747
Zhang J, Sin S-W, Liu Y, et al., 2023, On the Synthesis of Continuous-Time Sturdy MASH Delta-Sigma Modulators, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, Vol: 70, Pages: 356-360, ISSN: 1549-7747
Li Y, Zhao J, Liu Y, et al., 2023, A Comprehensive Study on the Design Methodology of Level Shifter Circuits, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, Vol: 70, Pages: 302-314, ISSN: 1549-8328
Liu H, Lin Y, Qi L, et al., 2022, Analysis and Design of VCO-Based Neural Front-End With Mixed Domain Level-Crossing for Fast Artifact Recovery, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, ISSN: 1549-8328
Liu H, Qi L, Wang G, et al., 2022, A VCO-Based CTDSM With Integrated Phase Error Correction for Neural Interface, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol: 69, Pages: 4018-4022, ISSN: 1549-7747
Neural recording front-ends with voltage controlled-oscillator (VCO) based continuous-time rm Delta Sigma modulators (CTDSM) enable direct analogue to digital conversion with minimized aliasing and hardware overhead, however, their performance suffers from phase glitches due to sampling meta-stability and large interference from input or power line. This brief presents a self-correction scheme for multi-phase VCO-based CTDSM. The VCO's phase pattern is processed in both continuous-time (CT) and discrete-time (DT) domain with real-time error detection and correction to guarantee robust operation. Based on the this scheme, a phase counter can be implemented to assist the XOR-based phase detector (PD) with minimized error, extending the phase detection range, therefore leading to improved quantization resolution and system linearity even with glitches. Fabricated in a 180-nm CMOS process, the prototype achieves 70.7 dB SNDR, 71.0 dB SNR, 83.1 dB SFDR and 71.2 dB DR within 10 kHz bandwidth. The measured input referred noise (IRN) is 5.94 mu text{V}rm -{rms} over 0.5 Hz-10 kHz bandwidth. The performance of this self-correction scheme is verified by injecting phase error with different frequency. A maximum of 16.2 dB improvement of SNDR can be observed for 625 Hz injected interference.
Liu H, Guo T, Yan P, et al., 2022, A Hybrid 1<sup>st</sup>/2<sup>nd</sup>-Order VCO-Based CTDSM With Rail-to-Rail Artifact Tolerance for Bidirectional Neural Interface, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol: 69, Pages: 2682-2686, ISSN: 1549-7747
Bi-directional brain machine interfaces enable simultaneous brain activity monitoring and neural modulation. However stimulation artifact can saturate instrumentation front-end, while concurrent on-site recording is needed. This brief presents a voltage controlled-oscillator (VCO) based continuous-time $\rm \Delta \Sigma $ modulator (CTDSM) with rail-to-rail input range and fast artifact tracking. A hybrid $1^{st}/2^{nd}$ -order loop is designed to achieve high dynamic range (DR) and large input range. Stimulation artifact is detected by a phase counter and compensated by the $1^{st}$ -order loop. The residue signal is digitized by the $2^{nd}$ -order loop for high precision. Redundancy between the two loops is implemented as feedback capacitors elements with non-binary ratio to guarantee feedback stability and linearity. Fabricated in a 55-nm CMOS process, the prototype achieves 65.7dB SNDR across 10 kHz bandwidth with a full scale of 200 mVpp. And a ±1.2 V input range is achieved to suppress artifacts. Saline based experiment with simultaneous stimulation and recording demonstrates that the implemented system can track and tolerate rail-to-rail stimulation artifact within 30 $\mu \text{s}$ while small neural signal can be continuously monitored.
Chen Y, Liu Y, Li Y, et al., 2022, An Energy-Efficient ASK Demodulator Robust to Power-Carrier-Interference for Inductive Power and Data Telemetry., IEEE Trans Biomed Circuits Syst, Vol: 16, Pages: 108-118
Wireless power and datatelemetry based on amplitude-shift keying (ASK) modulation over dual inductive links has been widely adopted in biomedical implants. Due to the mutual inductance between the power and data links, the large power-carrier-interference (PCI) will inevitably cause low signal-to-interference ratio (SIR) of the received signal, thereby increasing the bit-error-rate (BER) of the ASK demodulation. In this paper, an innovative high energy-efficient ASK demodulator robust to PCI has been proposed. Thanks to the proposed sampling-and-subtraction (SAS) architecture, the demodulator is capable of withstanding PCI with an amplitude up to 2.5 times as the data carrier without the need for any high-order filters. The prototype has been implemented with 180 nm standard CMOS process, occupying a core area of 0.51 mm 2. The experimental results show that with 1 Mbps data rate and 13.56 MHz carrier frequency, the typical BER is less than 1.3×10 -3, while the energy efficiency is 280 pJ/bit, showing 7.5× improvement compared to the prior works. The energy-efficient robustness to PCI demonstrates the potential of the technique to be applied to retina prostheses as well as various kinds of ultra-low-power implantable biomedical devices.
Huang J, Zhou T, Liu H, et al., 2022, Low-Noise, High-Linearity Sine-Wave Generation Using Noise-Shaping Phase-Switching Technique, IEEE Transactions on Instrumentation and Measurement, Vol: 71, ISSN: 0018-9456
To develop a lower cost on-chip characterization solution for postsilicon validation, this article proposed a 'noise-shaping phase-switching' technique on a sigma-delta modulated digital-to-analog converter (DAC) to realize a low-noise, high-linearity sinusoidal-wave generator. The proposed technique combines the fifth-order cascade of resonators with distributed feedback (CRFB) type delta-sigma modulation (DSM) and the two-way time-interleaving phase-switching harmonic distortion (HD) cancellation technique without additional cost. The theoretical analysis is verified with MATLAB and further implemented using a low-cost arbitrary waveform generator (AWG) as the output DAC. Compared with a nonideal 12-b DAC, the proposed technique achieved at least 2-dB enhancement in spurious-free dynamic range (SFDR) (measurement) while maintaining an improvement of at least 18 dB in the medium dynamic range (DR) (simulation) over the entire signal bandwidth.
Huang J, Zhou T, Wang C, et al., 2022, Design of a High Linearity Sinusoidal Current Generator Using Shifting Current Mirror Architecture, IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, Vol: 71, ISSN: 0018-9456
Pan L, Chen M, Chen Y, et al., 2021, An Energy-Autonomous Power-and-Data Telemetry Circuit With Digital-Assisted-PLL-Based BPSK Demodulator for Implantable Flexible Electronics Applications, IEEE OPEN JOURNAL OF CIRCUITS AND SYSTEMS, Vol: 2, Pages: 721-731
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Luo J, Firflionis D, Turnball M, et al., 2020, The neural engine: a reprogrammable low power platform for closed-loop optogenetics, IEEE Transactions on Biomedical Engineering, Vol: 67, Pages: 3004-3015, ISSN: 0018-9294
Brain-machine Interfaces (BMI) hold great potential for treating neurological disorders such as epilepsy. Technological progress is allowing for a shift from open-loop, pacemaker-class, intervention towards fully closed-loop neural control systems. Low power programmable processing systems are therefore required which can operate within the thermal window of 2° C for medical implants and maintain long battery life. In this work, we developed a low power neural engine with an optimized set of algorithms which can operate under a power cycling domain. By integrating with custom designed brain implant chip, we have demonstrated the operational applicability to the closed-loop modulating neural activities in in-vitro brain tissues: the local field potentials can be modulated at required central frequency ranges. Also, both a freely-moving non-human primate (24-hour) and a rodent (1-hour) in-vivo experiments were performed to show system long-term recording performance. The overall system consumes only 2.93mA during operation with a biological recording frequency 50Hz sampling rate (the lifespan is approximately 56 hours). A library of algorithms has been implemented in terms of detection, suppression and optical intervention to allow for exploratory applications in different neurological disorders. Thermal experiments demonstrated that operation creates minimal heating as well as battery performance exceeding 24 hours on a freely moving rodent. Therefore, this technology shows great capabilities for both neuroscience in-vitro/in-vivo applications and medical implantable processing units.
Williams I, Brunton E, Rapeaux A, et al., 2020, SenseBack-an implantable system for bidirectional neural interfacing, IEEE Transactions on Biomedical Circuits and Systems, Vol: 14, Pages: 1079-1087, ISSN: 1932-4545
Chronic in-vivo neurophysiology experiments require highly miniaturized, remotely powered multi-channel neural interfaces which are currently lacking in power or flexibility post implantation. In this article, to resolve this problem we present the SenseBack system, a post-implantation reprogrammable wireless 32-channel bidirectional neural interfacing that can enable chronic peripheral electrophysiology experiments in freely behaving small animals. The large number of channels for a peripheral neural interface, coupled with fully implantable hardware and complete software flexibility enable complex in-vivo studies where the system can adapt to evolving study needs as they arise. In complementary ex-vivo and in-vivo preparations, we demonstrate that this system can record neural signals and perform high-voltage, bipolar stimulation on any channel. In addition, we demonstrate transcutaneous power delivery and Bluetooth 5 data communication with a PC. The SenseBack system is capable of stimulation on any channel with ±20 V of compliance and up to 315 μA of current, and highly configurable recording with per-channel adjustable gain and filtering with 8 sets of 10-bit ADCs to sample data at 20 kHz for each channel. To the best of our knowledge this is the first such implantable research platform offering this level of performance and flexibility post-implantation (including complete reprogramming even after encapsulation) for small animal electrophysiology. Here we present initial acute trials, demonstrations and progress towards a system that we expect to enable a wide range of electrophysiology experiments in freely behaving animals.
Liu Y, Constandinou TG, Georgiou P, 2019, Ultrafast large-scale chemical sensing with CMOS ISFETs: a level-crossing time-domain approach, IEEE Transactions on Biomedical Circuits and Systems, Vol: 13, Pages: 1201-1213, ISSN: 1932-4545
The introduction of large-scale chemical sensing systems in CMOS which integrate millions of ISFET sensors have allowed applications such as DNA sequencing and fine-pixel chemical imaging systems to be realised. Using CMOS ISFETs provides advantages of digitisation directly at the sensor as well as correcting for non-linearity in its response. However, for this to be beneficial and scale, the readout circuits need to have the minimum possible footprint and power consumption. Within this context, this paper analyses an ISFET based pH-to-time readout using an inverter in the time-domain as a level-crossing detector and presents a 32×32 array with in-pixel digitisation for pH sensing. The inverter-based sensing pixel, controlled by a triangular waveform, converts the pH response into a time-domain signal whilst also compensating for sensor offset and thus resulting in an increase in dynamic range. The sensor pixels interface to a 15-bit asynchronous column-wise time-to-digital converter (TDC), enabling fast asynchronous conversion whilst using minimal silicon area. Parallel outputs of 32 TDC interfaces are serialised to achieve fast data throughput. This system is implemented in a standard 0.18um CMOS technology, with a pixel size of 26μm×26μm and a TDC area of 26μm×180μm. Measured results demonstrate the system is able to sense reliably with an average pH sensitivity of 30mVpH, whilst being able to compensate for sensor offset by up to ±7V. A resolution of 0.013pH is achieved and noise measurements show an integrated noise of 0.08pH within 2-500Hz and SFDR of 42.6dB. Total power consumption is 11.286mW.
Mirza KB, Kulasekeram N, Liu Y, et al., 2019, System on chip for closed loop neuromodulation based on dual mode biosignals, 2019 IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: Institute of Electrical and Electronics Engineers (IEEE), ISSN: 2158-1525
Closed loop neuromodulation, where the stimulation is controlled autonomously based on physiological events, has been more effective than open loop techniques. In the few existing closed loop implementations which have a feedback, indirect non-neurophysiological biomarkers have been typically used (e.g. heart rate, stomach distension). Although these biomarkers enable automatic initiation of neural stimulation, they do not enable intelligent control of stimulation dosage. In this paper, we present a novel closed loop neuromodulation System-on-Chip (SoC) based on a dual signal mode that is detecting both electrical and chemical signatures of neural activity. We use vagus nerve stimulation (VNS) as a design case here. Vagal chemical (pH) signal is detected and used for initiating VNS and vagal compound nerve action potential (CNAP) signals are used to determine the stimulation dosage and pattern. Although we used the paradigm of appetite control and neurometabolic therapies for developing the algorithms for neurostimulation control, the SoC described here can be utilised for other types of closed loop neuromodulation implants.
Mazza F, Liu Y, Donaldson N, et al., 2018, Integrated devices for micro-package integrity monitoring in mm-scale neural implants, IEEE Biomedical Circuits and Systems (BioCAS) Conference 2018, Publisher: IEEE, Pages: 295-298
Recent developments in the design of active im-plantable devices have achieved significant advances, for example,an increased number of recording channels, but too oftenpractical clinical applications are restricted by device longevity.It is important however to complement efforts for increased func-tionality with translational work to develop implant technologiesthat are safe and reliable to be hosted inside the human bodyover long periods of time. This paper first examines techniquescurrently used to evaluate micro-package hermeticity and keychallenges, highlighting the need for new,in situinstrumentationthat can monitor the encapsulation status over time. Two novelcircuits are then proposed to tackle the specific issue of moisturepenetration inside a sub-mm, silicon-based package. They bothshare the use of metal tracks on the different layers of the CMOSstack to measure changes in impedance caused by moisturepresent in leak cracks or diffused into the oxide layers.
Haci D, Liu Y, Nikolic K, et al., 2018, Thermally controlled lab-on-PCB for biomedical applications, IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 655-658
This paper reports on the implementation andcharacterisation of a thermally controlled device forin vitrobiomedical applications, based on standard Printed Circuit Board(PCB) technology. This is proposed as a low cost alternativeto state-of-the-art microfluidic devices and Lab-on-Chip (LoC)platforms, which we refer to as the thermal Lab-on-PCB concept.In total, six different prototype boards have been manufacturedto implement as many mini-hotplate arrays. 3D multiphysicssoftware simulations show the thermal response of the modelledmini-hotplate boards to electrical current stimulation, highlight-ing their versatile heating capability. A comparison with theresults obtained by the characterisation of the fabricated PCBsdemonstrates the dual temperature sensing/heating property ofthe mini-hotplate, exploitable in a larger range of temperaturewith respect to the typical operating range of LoC devices. Thethermal system is controllable by means of external off-the-shelfcircuitry designed and implemented on a single-channel controlboard prototype.
Haci D, Liu Y, Ghoreishizadeh S, et al., 2018, Design considerations for ground referencing in multi-module neural implants, IEEE Biomedical Circuits and Systems (BioCAS) Conference 2018, Publisher: IEEE, Pages: 563-566
Implantable neural interfaces have evolved in thepast decades from stimulation-only devices to closed-loop record-ing and stimulation systems, allowing both for more targetedtherapeutic techniques and more advanced prosthetic implants.Emerging applications require multi-module active implantabledevices with intrabody power and data transmission. Thisdistributed approach poses a new set of challenges relatedto inter-module connectivity, functional reliability and patientsafety. This paper addresses the ground referencing challenge inactive multi-implant systems, with a particular focus on neuralrecording devices. Three different grounding schemes (passive,drive, and sense) are presented and evaluated in terms of bothrecording reliability and patient safety. Considerations on thepractical implementation of body potential referencing circuitryare finally discussed, with a detailed analysis of their impact onthe recording performance.
Luan S, Williams I, Maslik M, et al., 2018, Compact standalone platform for neural recording with real-time spike sorting and data logging, Journal of Neural Engineering, Vol: 15, Pages: 1-13, ISSN: 1741-2552
Objective. Longitudinal observation of single unit neural activity from largenumbers of cortical neurons in awake and mobile animals is often a vital step in studying neural network behaviour and towards the prospect of building effective Brain Machine Interfaces (BMIs). These recordings generate enormous amounts of data for transmission & storage, and typically require o ine processing to tease out the behaviour of individual neurons. Our aim was to create a compact system capable of: 1) reducing the data bandwidth by circa 2 to 3 orders of magnitude (greatly improving battery lifetime and enabling low power wireless transmission in future versions); 2) producing real-time, low-latency, spike sorted data; and 3) long term untethered operation. Approach. We have developed a headstage that operates in two phases. In the short training phase a computer is attached and classic spike sorting is performed to generate templates. In the second phase the system is untethered and performs template matching to create an event driven spike output that is logged to a micro-SD card. To enable validation the system is capable of logging the high bandwidth raw neural signal data as well as the spike sorted data. Main results. The system can successfully record 32 channels of raw neural signal data and/or spike sorted events for well over 24 hours at a time and is robust to power dropouts during battery changes as well as SD card replacement. A 24-hour initial recording in a nonhuman primate M1 showed consistent spike shapes with the expected changes in neural activity during awake behaviour and sleep cycles. Signi cance The presented platform allows neural activity to be unobtrusively monitored and processed in real-time in freely behaving untethered animals { revealing insights that are not attainable through scheduled recording sessions. This system achieves the lowest power per channel to date and provides a robust, low-latency, low-bandwidth and veri able output suitable f
Maslik M, Liu Y, Lande TS, et al., 2018, Continuous-time acquisition of biosignals using a charge-based ADC topology, IEEE Transactions on Biomedical Circuits and Systems, Vol: 12, Pages: 471-482, ISSN: 1932-4545
This paper investigates continuous-time (CT) signal acquisition as an activity-dependent and nonuniform sampling alternative to conventional fixed-rate digitisation. We demonstrate the applicability to biosignal representation by quantifying the achievable bandwidth saving by nonuniform quantisation to commonly recorded biological signal fragments allowing a compression ratio of ≈5 and 26 when applied to electrocardiogram and extracellular action potential signals, respectively. We describe several desirable properties of CT sampling, including bandwidth reduction, elimination/reduction of quantisation error, and describe its impact on aliasing. This is followed by demonstration of a resource-efficient hardware implementation. We propose a novel circuit topology for a charge-based CT analogue-to-digital converter that has been optimized for the acquisition of neural signals. This has been implemented in a commercially available 0.35 μm CMOS technology occupying a compact footprint of 0.12 mm 2 . Silicon verified measurements demonstrate an 8-bit resolution and a 4 kHz bandwidth with static power consumption of 3.75 μW from a 1.5 V supply. The dynamic power dissipation is completely activity-dependent, requiring 1.39 pJ energy per conversion.
Ramezani R, Liu Y, Dehkhoda F, et al., 2018, On-probe neural interface ASIC for combined electrical recording and optogenetic stimulation, IEEE Transactions on Biomedical Circuits and Systems, Vol: 12, Pages: 576-588, ISSN: 1932-4545
Neuromodulation technologies are progressing from pacemaking and sensory operations to full closed-loop control. In particular, optogenetics—the genetic modification of light sensitivity into neural tissue allows for simultaneous optical stimulation and electronic recording. This paper presents a neural interface application-specified integrated circuit (ASIC) for intelligent optoelectronic probes. The architecture is designed to enable simultaneous optical neural stimulation and electronic recording. It provides four low noise (2.08 μVrms) recording channels optimized for recording local field potentials (LFPs) (0.1–300 Hz bandwidth, ± 5 mV range, sampled 10-bit@4 kHz), which are more stable for chronic applications. For stimulation, it provides six independently addressable optical driver circuits, which can provide both intensity (8-bit resolution across a 1.1 mA range) and pulse-width modulation for high-radiance light emitting diodes (LEDs). The system includes a fully digital interface using a serial peripheral interface (SPI) protocol to allow for use with embedded controllers. The SPI interface is embedded within a finite state machine (FSM), which implements a command interpreter that can send out LFP data whilst receiving instructions to control LED emission. The circuit has been implemented in a commercially available 0.35 μm CMOS technology occupying a 1.95 mm × 1.10 mm footprint for mounting onto the head of a silicon probe. Measured results are given for a variety of bench-top, in vitro and in vivo experiments, quantifying system performance and also demonstrating concurrent recording and stimulation within relevant experimental models.
Liu Y, Pereira J, Constandinou TG, 2018, Event-driven processing for hardware-efficient neural spike sorting, Journal of Neural Engineering, Vol: 15, Pages: 1-14, ISSN: 1741-2552
Objective. The prospect of real-time and on-node spike sorting provides a genuine opportunity to push the envelope of large-scale integrated neural recording systems. In such systems the hardware resources, power requirements and data bandwidth increase linearly with channel count. Event-based (or data-driven) processing can provide here a new efficient means for hardware implementation that is completely activity dependant. In this work, we investigate using continuous-time level-crossing sampling for efficient data representation and subsequent spike processing. Approach. (1) We first compare signals (synthetic neural datasets) encoded with this technique against conventional sampling. (2) We then show how such a representation can be directly exploited by extracting simple time domain features from the bitstream to perform neural spike sorting. (3) The proposed method is implemented in a low power FPGA platform to demonstrate its hardware viability. Main results. It is observed that considerably lower data rates are achievable when using 7 bits or less to represent the signals, whilst maintaining the signal fidelity. Results obtained using both MATLAB and reconfigurable logic hardware (FPGA) indicate that feature extraction and spike sorting accuracies can be achieved with comparable or better accuracy than reference methods whilst also requiring relatively low hardware resources. Significance. By effectively exploiting continuous-time data representation, neural signal processing can be achieved in a completely event-driven manner, reducing both the required resources (memory, complexity) and computations (operations). This will see future large-scale neural systems integrating on-node processing in real-time hardware.
Liu Y, Luan S, Williams I, et al., 2017, A 64-Channel Versatile Neural Recording SoC with Activity Dependant Data Throughput, IEEE Transactions on Biomedical Circuits and Systems, Vol: 11, Pages: 1344-1355, ISSN: 1932-4545
Modern microtechnology is enabling the channel count of neural recording integrated circuits to scale exponentially. However, the raw data bandwidth of these systems is increasing proportionately, presenting major challenges in terms of power consumption and data transmission (especially for wireless systems). This paper presents a system that exploits the sparse nature of neural signals to address these challenges and provides a reconfigurable low-bandwidth event-driven output. Specifically, we present a novel 64-channel low noise (2.1μVrms, low power (23μW per analogue channel) neural recording system-on-chip (SoC). This features individually-configurable channels, 10-bit analogue-to-digital conversion, digital filtering, spike detection, and an event-driven output. Each channel's gain, bandwidth & sampling rate settings can be independently configured to extract Local Field Potentials (LFPs) at a low data-rate and/or Action Potentials (APs) at a higher data rate. The sampled data is streamed through an SRAM buffer that supports additional on-chip processing such as digital filtering and spike detection. Real-time spike detection can achieve ~2 orders of magnitude data reduction, by using a dual polarity simple threshold to enable an event driven output for neural spikes (16-sample window). The SoC additionally features a latency-encoded asynchronous output that is critical if used as part of a closed-loop system. This has been specifically developed to complement a separate on-node spike sorting co-processor to provide a real-time (low latency) output. The system has been implemented in a commercially-available 0.35μm CMOS technology occupying a silicon area of 19.1mm² (0.3mm² gross per channel), demonstrating a low power & efficient architecture which could be further optimised by aggressive technology and supply voltage scaling.
Luo J, Firfilionis D, Ramezani R, et al., 2017, Live demonstration: a closed-loop cortical brain implant for optogenetic curing epilepsy, IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 169-169
Maslik M, Liu Y, Lande TS, et al., 2017, A charge-based ultra-low power continuous-time ADC for data driven neural spike processing, IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 1420-1423
The paper presents a novel topology of a continuous-time analogue-to-digital converter (CT-ADC) featuring ultra-low static power consumption, activity-dependent dynamic consumption, and a compact footprint. This is achieved by utilising a novel charge-packet based threshold generation method, that alleviates the requirement for a conventional feedback DAC. The circuit has a static power consumption of 3.75uW, with dynamic energy of 1.39pJ/conversion level. This type of converter is thus particularly well-suited for biosignals that are generally sparse in nature. The circuit has been optimised for neural spike recording by capturing a 3kHz bandwidth with 8-bit resolution. For a typical extracellular neural recording the average power consumption is in the order of ~4uW. The circuit has been implemented in a commercially available 0.35um CMOS technology with core occupying a footprint of 0.12 sq.mm
Haci D, Liu Y, Constandinou TG, 2017, 32-channel ultra-low-noise arbitrary signal generation platform for biopotential emulation, IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 698-701
This paper presents a multichannel, ultra-low-noise arbitrary signal generation platform for emulating a wide range of different biopotential signals (e.g. ECG, EEG, etc). This is intended for use in the test, measurement and demonstration of bioinstrumentation and medical devices that interface to electrode inputs. The system is organized in 3 key blocks for generating, processing and converting the digital data into a parallel high performance analogue output. These blocks consist of: (1) a Raspberry Pi 3 (RPi3) board; (2) a custom Field Programmable Gate Array (FPGA) board with low-power IGLOO Nano device; and (3) analogue board including the Digital-to-Analogue Converters (DACs) and output circuits. By implementing the system this way, good isolation can be achieved between the different power and signal domains. This mixed-signal architecture takes in a high bitrate SDIO (Secure Digital Input Output) stream, recodes and packetizes this to drive two multichannel DACs, with parallel analogue outputs that are then attenuated and filtered. The system achieves 32-parallel output channels each sampled at 48kS/s, with a 10kHz bandwidth, 110dB dynamic range and uV-level output noise.
Gao C, Ghoreishizadeh S, Liu Y, et al., 2017, On-chip ID generation for multi-node implantable devices using SA-PUF, IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 678-681
This paper presents a 64-bit on-chip identification system featuring low power consumption and randomness compensation for multi-node bio-implantable devices. A sense amplifier based bit-cell is proposed to realize the silicon physical unclonable function, providing a unique value whose probability has a uniform distribution and minimized influence from the temperature and supply variation. The entire system is designed and implemented in a typical 0.35 m CMOS technology, including an array of 64 bit-cells, readout circuits, and digital controllers for data interfaces. Simulated results show that the proposed bit-cell design achieved a uniformity of 50.24% and a uniqueness of 50.03% for generated IDs. The system achieved an energy consumption of 6.0 pJ per bit with parallel outputs and 17.3 pJ per bit with serial outputs.
Ghoreishizadeh S, Haci D, Liu Y, et al., 2017, Four-Wire Interface ASIC for a Multi-Implant Link, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol: 64, Pages: 3056-3067, ISSN: 1549-8328
This paper describes an on-chip interface for recovering power and providing full-duplex communication over an AC-coupled 4-wire lead between active implantable devices. The target application requires two modules to be implanted in the brain (cortex) and upper chest; connected via a subcutaneous lead. The brain implant consists of multiple identical ‘optrodes’ that facilitate a bidirectional neural interface (electrical recording, optical stimulation), and chest implant contains the power source (battery) and processor module. The proposed interface is integrated within each optrode ASIC allowing full-duplex and fully-differential communication based on Manchester encoding. The system features a head-to-chest uplink data rate(up to 1.6 Mbps) that is higher than that of the chest-to-head downlink (100 kbps) which is superimposed on a power carrier. On-chip power management provides an unregulated 5V DC supply with up to 2.5mA output current for stimulation, and two regulated voltages (3.3V and 3V) with 60 dB PSRR for recording and logic circuits. The 4-wire ASIC has been implemented in a 0.35 um CMOS technology, occupying 1.5mm2 silicon area,and consumes a quiescent current of 91.2u A. The system allows power transmission with measured efficiency of up to 66% from the chest to the brain implant. The downlink and uplink communication are successfully tested in a system with two optrodes and through a 4-wire implantable lead.
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