Imperial College London

DrYanLiu

Faculty of EngineeringDepartment of Electrical and Electronic Engineering

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Electrical EngineeringSouth Kensington Campus

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Publications

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32 results found

Luo J, Firflionis D, Turnball M, Xu W, Walsh D, Escobedo-Cousin E, Soltan A, Ramezani R, Liu Y, Bailey R, O'Neill A, Donaldson N, Constandinou T, Jackson A, Degenaar Pet al., 2020, The neural engine: a reprogrammable low power platform for closed-loop optogenetics, IEEE Transactions on Biomedical Engineering, Vol: 67, Pages: 3004-3015, ISSN: 0018-9294

Brain-machine Interfaces (BMI) hold great potential for treating neurological disorders such as epilepsy. Technological progress is allowing for a shift from open-loop, pacemaker-class, intervention towards fully closed-loop neural control systems. Low power programmable processing systems are therefore required which can operate within the thermal window of 2° C for medical implants and maintain long battery life. In this work, we developed a low power neural engine with an optimized set of algorithms which can operate under a power cycling domain. By integrating with custom designed brain implant chip, we have demonstrated the operational applicability to the closed-loop modulating neural activities in in-vitro brain tissues: the local field potentials can be modulated at required central frequency ranges. Also, both a freely-moving non-human primate (24-hour) and a rodent (1-hour) in-vivo experiments were performed to show system long-term recording performance. The overall system consumes only 2.93mA during operation with a biological recording frequency 50Hz sampling rate (the lifespan is approximately 56 hours). A library of algorithms has been implemented in terms of detection, suppression and optical intervention to allow for exploratory applications in different neurological disorders. Thermal experiments demonstrated that operation creates minimal heating as well as battery performance exceeding 24 hours on a freely moving rodent. Therefore, this technology shows great capabilities for both neuroscience in-vitro/in-vivo applications and medical implantable processing units.

Journal article

Williams I, Brunton E, Rapeaux A, Liu Y, Luan S, Nazarpour K, Constandinou TGet al., 2020, SenseBack-an implantable system for bidirectional neural interfacing, IEEE Transactions on Biomedical Circuits and Systems, Vol: 14, Pages: 1079-1087, ISSN: 1932-4545

Chronic in-vivo neurophysiology experiments require highly miniaturized, remotely powered multi-channel neural interfaces which are currently lacking in power or flexibility post implantation. In this article, to resolve this problem we present the SenseBack system, a post-implantation reprogrammable wireless 32-channel bidirectional neural interfacing that can enable chronic peripheral electrophysiology experiments in freely behaving small animals. The large number of channels for a peripheral neural interface, coupled with fully implantable hardware and complete software flexibility enable complex in-vivo studies where the system can adapt to evolving study needs as they arise. In complementary ex-vivo and in-vivo preparations, we demonstrate that this system can record neural signals and perform high-voltage, bipolar stimulation on any channel. In addition, we demonstrate transcutaneous power delivery and Bluetooth 5 data communication with a PC. The SenseBack system is capable of stimulation on any channel with ±20 V of compliance and up to 315 μA of current, and highly configurable recording with per-channel adjustable gain and filtering with 8 sets of 10-bit ADCs to sample data at 20 kHz for each channel. To the best of our knowledge this is the first such implantable research platform offering this level of performance and flexibility post-implantation (including complete reprogramming even after encapsulation) for small animal electrophysiology. Here we present initial acute trials, demonstrations and progress towards a system that we expect to enable a wide range of electrophysiology experiments in freely behaving animals.

Journal article

Liu Y, Constandinou TG, Georgiou P, 2019, Ultrafast large-scale chemical sensing with CMOS ISFETs: a level-crossing time-domain approach, IEEE Transactions on Biomedical Circuits and Systems, Vol: 13, Pages: 1201-1213, ISSN: 1932-4545

The introduction of large-scale chemical sensing systems in CMOS which integrate millions of ISFET sensors have allowed applications such as DNA sequencing and fine-pixel chemical imaging systems to be realised. Using CMOS ISFETs provides advantages of digitisation directly at the sensor as well as correcting for non-linearity in its response. However, for this to be beneficial and scale, the readout circuits need to have the minimum possible footprint and power consumption. Within this context, this paper analyses an ISFET based pH-to-time readout using an inverter in the time-domain as a level-crossing detector and presents a 32×32 array with in-pixel digitisation for pH sensing. The inverter-based sensing pixel, controlled by a triangular waveform, converts the pH response into a time-domain signal whilst also compensating for sensor offset and thus resulting in an increase in dynamic range. The sensor pixels interface to a 15-bit asynchronous column-wise time-to-digital converter (TDC), enabling fast asynchronous conversion whilst using minimal silicon area. Parallel outputs of 32 TDC interfaces are serialised to achieve fast data throughput. This system is implemented in a standard 0.18um CMOS technology, with a pixel size of 26μm×26μm and a TDC area of 26μm×180μm. Measured results demonstrate the system is able to sense reliably with an average pH sensitivity of 30mVpH, whilst being able to compensate for sensor offset by up to ±7V. A resolution of 0.013pH is achieved and noise measurements show an integrated noise of 0.08pH within 2-500Hz and SFDR of 42.6dB. Total power consumption is 11.286mW.

Journal article

Mirza KB, Kulasekeram N, Liu Y, Nikolic K, Toumazou Cet al., 2019, System on chip for closed loop neuromodulation based on dual mode biosignals, 2019 IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: Institute of Electrical and Electronics Engineers (IEEE), ISSN: 2158-1525

Closed loop neuromodulation, where the stimulation is controlled autonomously based on physiological events, has been more effective than open loop techniques. In the few existing closed loop implementations which have a feedback, indirect non-neurophysiological biomarkers have been typically used (e.g. heart rate, stomach distension). Although these biomarkers enable automatic initiation of neural stimulation, they do not enable intelligent control of stimulation dosage. In this paper, we present a novel closed loop neuromodulation System-on-Chip (SoC) based on a dual signal mode that is detecting both electrical and chemical signatures of neural activity. We use vagus nerve stimulation (VNS) as a design case here. Vagal chemical (pH) signal is detected and used for initiating VNS and vagal compound nerve action potential (CNAP) signals are used to determine the stimulation dosage and pattern. Although we used the paradigm of appetite control and neurometabolic therapies for developing the algorithms for neurostimulation control, the SoC described here can be utilised for other types of closed loop neuromodulation implants.

Conference paper

Mazza F, Liu Y, Donaldson N, Constandinou TGet al., 2018, Integrated devices for micro-package integrity monitoring in mm-scale neural implants, IEEE Biomedical Circuits and Systems (BioCAS) Conference 2018, Publisher: IEEE, Pages: 295-298

Recent developments in the design of active im-plantable devices have achieved significant advances, for example,an increased number of recording channels, but too oftenpractical clinical applications are restricted by device longevity.It is important however to complement efforts for increased func-tionality with translational work to develop implant technologiesthat are safe and reliable to be hosted inside the human bodyover long periods of time. This paper first examines techniquescurrently used to evaluate micro-package hermeticity and keychallenges, highlighting the need for new,in situinstrumentationthat can monitor the encapsulation status over time. Two novelcircuits are then proposed to tackle the specific issue of moisturepenetration inside a sub-mm, silicon-based package. They bothshare the use of metal tracks on the different layers of the CMOSstack to measure changes in impedance caused by moisturepresent in leak cracks or diffused into the oxide layers.

Conference paper

Haci D, Liu Y, Nikolic K, Demarchi D, Constandinou TG, Georgiou Pet al., 2018, Thermally controlled lab-on-PCB for biomedical applications, IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 655-658

This paper reports on the implementation andcharacterisation of a thermally controlled device forin vitrobiomedical applications, based on standard Printed Circuit Board(PCB) technology. This is proposed as a low cost alternativeto state-of-the-art microfluidic devices and Lab-on-Chip (LoC)platforms, which we refer to as the thermal Lab-on-PCB concept.In total, six different prototype boards have been manufacturedto implement as many mini-hotplate arrays. 3D multiphysicssoftware simulations show the thermal response of the modelledmini-hotplate boards to electrical current stimulation, highlight-ing their versatile heating capability. A comparison with theresults obtained by the characterisation of the fabricated PCBsdemonstrates the dual temperature sensing/heating property ofthe mini-hotplate, exploitable in a larger range of temperaturewith respect to the typical operating range of LoC devices. Thethermal system is controllable by means of external off-the-shelfcircuitry designed and implemented on a single-channel controlboard prototype.

Conference paper

Haci D, Liu Y, Ghoreishizadeh S, Constandinou TGet al., 2018, Design considerations for ground referencing in multi-module neural implants, IEEE Biomedical Circuits and Systems (BioCAS) Conference 2018, Publisher: IEEE, Pages: 563-566

Implantable neural interfaces have evolved in thepast decades from stimulation-only devices to closed-loop record-ing and stimulation systems, allowing both for more targetedtherapeutic techniques and more advanced prosthetic implants.Emerging applications require multi-module active implantabledevices with intrabody power and data transmission. Thisdistributed approach poses a new set of challenges relatedto inter-module connectivity, functional reliability and patientsafety. This paper addresses the ground referencing challenge inactive multi-implant systems, with a particular focus on neuralrecording devices. Three different grounding schemes (passive,drive, and sense) are presented and evaluated in terms of bothrecording reliability and patient safety. Considerations on thepractical implementation of body potential referencing circuitryare finally discussed, with a detailed analysis of their impact onthe recording performance.

Conference paper

Luan S, Williams I, Maslik M, Liu Y, De Carvalho F, Jackson A, Quian Quiroga R, Constandinou Tet al., 2018, Compact standalone platform for neural recording with real-time spike sorting and data logging, Journal of Neural Engineering, Vol: 15, Pages: 1-13, ISSN: 1741-2552

Objective. Longitudinal observation of single unit neural activity from largenumbers of cortical neurons in awake and mobile animals is often a vital step in studying neural network behaviour and towards the prospect of building effective Brain Machine Interfaces (BMIs). These recordings generate enormous amounts of data for transmission & storage, and typically require o ine processing to tease out the behaviour of individual neurons. Our aim was to create a compact system capable of: 1) reducing the data bandwidth by circa 2 to 3 orders of magnitude (greatly improving battery lifetime and enabling low power wireless transmission in future versions); 2) producing real-time, low-latency, spike sorted data; and 3) long term untethered operation. Approach. We have developed a headstage that operates in two phases. In the short training phase a computer is attached and classic spike sorting is performed to generate templates. In the second phase the system is untethered and performs template matching to create an event driven spike output that is logged to a micro-SD card. To enable validation the system is capable of logging the high bandwidth raw neural signal data as well as the spike sorted data. Main results. The system can successfully record 32 channels of raw neural signal data and/or spike sorted events for well over 24 hours at a time and is robust to power dropouts during battery changes as well as SD card replacement. A 24-hour initial recording in a nonhuman primate M1 showed consistent spike shapes with the expected changes in neural activity during awake behaviour and sleep cycles. Signi cance The presented platform allows neural activity to be unobtrusively monitored and processed in real-time in freely behaving untethered animals { revealing insights that are not attainable through scheduled recording sessions. This system achieves the lowest power per channel to date and provides a robust, low-latency, low-bandwidth and veri able output suitable f

Journal article

Maslik M, Liu Y, Lande TS, Constandinou TGet al., 2018, Continuous-time acquisition of biosignals using a charge-based ADC topology, IEEE Transactions on Biomedical Circuits and Systems, Vol: 12, Pages: 471-482, ISSN: 1932-4545

This paper investigates continuous-time (CT) signal acquisition as an activity-dependent and nonuniform sampling alternative to conventional fixed-rate digitisation. We demonstrate the applicability to biosignal representation by quantifying the achievable bandwidth saving by nonuniform quantisation to commonly recorded biological signal fragments allowing a compression ratio of ≈5 and 26 when applied to electrocardiogram and extracellular action potential signals, respectively. We describe several desirable properties of CT sampling, including bandwidth reduction, elimination/reduction of quantisation error, and describe its impact on aliasing. This is followed by demonstration of a resource-efficient hardware implementation. We propose a novel circuit topology for a charge-based CT analogue-to-digital converter that has been optimized for the acquisition of neural signals. This has been implemented in a commercially available 0.35 μm CMOS technology occupying a compact footprint of 0.12 mm 2 . Silicon verified measurements demonstrate an 8-bit resolution and a 4 kHz bandwidth with static power consumption of 3.75 μW from a 1.5 V supply. The dynamic power dissipation is completely activity-dependent, requiring 1.39 pJ energy per conversion.

Journal article

Ramezani R, Liu Y, Dehkhoda F, Soltan A, Haci D, Zhao H, Hazra A, Cunningham M, Firfilionis D, Jackson A, Constandinou TG, Degenaar Pet al., 2018, On-probe neural interface ASIC for combined electrical recording and optogenetic stimulation, IEEE Transactions on Biomedical Circuits and Systems, Vol: 12, Pages: 576-588, ISSN: 1932-4545

Neuromodulation technologies are progressing from pacemaking and sensory operations to full closed-loop control. In particular, optogenetics—the genetic modification of light sensitivity into neural tissue allows for simultaneous optical stimulation and electronic recording. This paper presents a neural interface application-specified integrated circuit (ASIC) for intelligent optoelectronic probes. The architecture is designed to enable simultaneous optical neural stimulation and electronic recording. It provides four low noise (2.08 μVrms) recording channels optimized for recording local field potentials (LFPs) (0.1–300 Hz bandwidth, ± 5 mV range, sampled 10-bit@4 kHz), which are more stable for chronic applications. For stimulation, it provides six independently addressable optical driver circuits, which can provide both intensity (8-bit resolution across a 1.1 mA range) and pulse-width modulation for high-radiance light emitting diodes (LEDs). The system includes a fully digital interface using a serial peripheral interface (SPI) protocol to allow for use with embedded controllers. The SPI interface is embedded within a finite state machine (FSM), which implements a command interpreter that can send out LFP data whilst receiving instructions to control LED emission. The circuit has been implemented in a commercially available 0.35 μm CMOS technology occupying a 1.95 mm × 1.10 mm footprint for mounting onto the head of a silicon probe. Measured results are given for a variety of bench-top, in vitro and in vivo experiments, quantifying system performance and also demonstrating concurrent recording and stimulation within relevant experimental models.

Journal article

Liu Y, Pereira J, Constandinou TG, 2018, Event-driven processing for hardware-efficient neural spike sorting, Journal of Neural Engineering, Vol: 15, Pages: 1-14, ISSN: 1741-2552

Objective. The prospect of real-time and on-node spike sorting provides a genuine opportunity to push the envelope of large-scale integrated neural recording systems. In such systems the hardware resources, power requirements and data bandwidth increase linearly with channel count. Event-based (or data-driven) processing can provide here a new efficient means for hardware implementation that is completely activity dependant. In this work, we investigate using continuous-time level-crossing sampling for efficient data representation and subsequent spike processing. Approach. (1) We first compare signals (synthetic neural datasets) encoded with this technique against conventional sampling. (2) We then show how such a representation can be directly exploited by extracting simple time domain features from the bitstream to perform neural spike sorting. (3) The proposed method is implemented in a low power FPGA platform to demonstrate its hardware viability. Main results. It is observed that considerably lower data rates are achievable when using 7 bits or less to represent the signals, whilst maintaining the signal fidelity. Results obtained using both MATLAB and reconfigurable logic hardware (FPGA) indicate that feature extraction and spike sorting accuracies can be achieved with comparable or better accuracy than reference methods whilst also requiring relatively low hardware resources. Significance. By effectively exploiting continuous-time data representation, neural signal processing can be achieved in a completely event-driven manner, reducing both the required resources (memory, complexity) and computations (operations). This will see future large-scale neural systems integrating on-node processing in real-time hardware.

Journal article

Liu Y, Luan S, Williams I, Rapeaux A, Constandinou TGet al., 2017, A 64-Channel Versatile Neural Recording SoC with Activity Dependant Data Throughput, IEEE Transactions on Biomedical Circuits and Systems, Vol: 11, Pages: 1344-1355, ISSN: 1932-4545

Modern microtechnology is enabling the channel count of neural recording integrated circuits to scale exponentially. However, the raw data bandwidth of these systems is increasing proportionately, presenting major challenges in terms of power consumption and data transmission (especially for wireless systems). This paper presents a system that exploits the sparse nature of neural signals to address these challenges and provides a reconfigurable low-bandwidth event-driven output. Specifically, we present a novel 64-channel low noise (2.1μVrms, low power (23μW per analogue channel) neural recording system-on-chip (SoC). This features individually-configurable channels, 10-bit analogue-to-digital conversion, digital filtering, spike detection, and an event-driven output. Each channel's gain, bandwidth & sampling rate settings can be independently configured to extract Local Field Potentials (LFPs) at a low data-rate and/or Action Potentials (APs) at a higher data rate. The sampled data is streamed through an SRAM buffer that supports additional on-chip processing such as digital filtering and spike detection. Real-time spike detection can achieve ~2 orders of magnitude data reduction, by using a dual polarity simple threshold to enable an event driven output for neural spikes (16-sample window). The SoC additionally features a latency-encoded asynchronous output that is critical if used as part of a closed-loop system. This has been specifically developed to complement a separate on-node spike sorting co-processor to provide a real-time (low latency) output. The system has been implemented in a commercially-available 0.35μm CMOS technology occupying a silicon area of 19.1mm² (0.3mm² gross per channel), demonstrating a low power & efficient architecture which could be further optimised by aggressive technology and supply voltage scaling.

Journal article

Luo J, Firfilionis D, Ramezani R, Dehkhoda F, Soltan A, Degenaar P, Liu Y, Constandinou TGet al., 2017, Live demonstration: a closed-loop cortical brain implant for optogenetic curing epilepsy, IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 169-169

Conference paper

Gao C, Ghoreishizadeh S, Liu Y, Constandinou TGet al., 2017, On-chip ID generation for multi-node implantable devices using SA-PUF, IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 678-681

This paper presents a 64-bit on-chip identification system featuring low power consumption and randomness compensation for multi-node bio-implantable devices. A sense amplifier based bit-cell is proposed to realize the silicon physical unclonable function, providing a unique value whose probability has a uniform distribution and minimized influence from the temperature and supply variation. The entire system is designed and implemented in a typical 0.35 m CMOS technology, including an array of 64 bit-cells, readout circuits, and digital controllers for data interfaces. Simulated results show that the proposed bit-cell design achieved a uniformity of 50.24% and a uniqueness of 50.03% for generated IDs. The system achieved an energy consumption of 6.0 pJ per bit with parallel outputs and 17.3 pJ per bit with serial outputs.

Conference paper

Maslik M, Liu Y, Lande TS, Constandinou TGet al., 2017, A charge-based ultra-low power continuous-time ADC for data driven neural spike processing, IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 1420-1423

The paper presents a novel topology of a continuous-time analogue-to-digital converter (CT-ADC) featuring ultra-low static power consumption, activity-dependent dynamic consumption, and a compact footprint. This is achieved by utilising a novel charge-packet based threshold generation method, that alleviates the requirement for a conventional feedback DAC. The circuit has a static power consumption of 3.75uW, with dynamic energy of 1.39pJ/conversion level. This type of converter is thus particularly well-suited for biosignals that are generally sparse in nature. The circuit has been optimised for neural spike recording by capturing a 3kHz bandwidth with 8-bit resolution. For a typical extracellular neural recording the average power consumption is in the order of ~4uW. The circuit has been implemented in a commercially available 0.35um CMOS technology with core occupying a footprint of 0.12 sq.mm

Conference paper

Haci D, Liu Y, Constandinou TG, 2017, 32-channel ultra-low-noise arbitrary signal generation platform for biopotential emulation, IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 698-701

This paper presents a multichannel, ultra-low-noise arbitrary signal generation platform for emulating a wide range of different biopotential signals (e.g. ECG, EEG, etc). This is intended for use in the test, measurement and demonstration of bioinstrumentation and medical devices that interface to electrode inputs. The system is organized in 3 key blocks for generating, processing and converting the digital data into a parallel high performance analogue output. These blocks consist of: (1) a Raspberry Pi 3 (RPi3) board; (2) a custom Field Programmable Gate Array (FPGA) board with low-power IGLOO Nano device; and (3) analogue board including the Digital-to-Analogue Converters (DACs) and output circuits. By implementing the system this way, good isolation can be achieved between the different power and signal domains. This mixed-signal architecture takes in a high bitrate SDIO (Secure Digital Input Output) stream, recodes and packetizes this to drive two multichannel DACs, with parallel analogue outputs that are then attenuated and filtered. The system achieves 32-parallel output channels each sampled at 48kS/s, with a 10kHz bandwidth, 110dB dynamic range and uV-level output noise.

Conference paper

Ghoreishizadeh S, Haci D, Liu Y, Donaldson N, Constandinou TGet al., 2017, Four-Wire Interface ASIC for a Multi-Implant Link, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol: 64, Pages: 3056-3067, ISSN: 1549-8328

This paper describes an on-chip interface for recovering power and providing full-duplex communication over an AC-coupled 4-wire lead between active implantable devices. The target application requires two modules to be implanted in the brain (cortex) and upper chest; connected via a subcutaneous lead. The brain implant consists of multiple identical ‘optrodes’ that facilitate a bidirectional neural interface (electrical recording, optical stimulation), and chest implant contains the power source (battery) and processor module. The proposed interface is integrated within each optrode ASIC allowing full-duplex and fully-differential communication based on Manchester encoding. The system features a head-to-chest uplink data rate(up to 1.6 Mbps) that is higher than that of the chest-to-head downlink (100 kbps) which is superimposed on a power carrier. On-chip power management provides an unregulated 5V DC supply with up to 2.5mA output current for stimulation, and two regulated voltages (3.3V and 3V) with 60 dB PSRR for recording and logic circuits. The 4-wire ASIC has been implemented in a 0.35 um CMOS technology, occupying 1.5mm2 silicon area,and consumes a quiescent current of 91.2u A. The system allows power transmission with measured efficiency of up to 66% from the chest to the brain implant. The downlink and uplink communication are successfully tested in a system with two optrodes and through a 4-wire implantable lead.

Journal article

Ghoreishizadeh S, Haci D, Liu Y, Constandinou Tet al., 2017, A 4-wire interface SoC for shared multi-implant power transfer and full-duplex communication, IEEE Latin American symposium on Circuits and Systems (LASCAS), Publisher: IEEE, Pages: 49-52, ISSN: 2473-4667

This paper describes a novel system for recovering power and providing full-duplex communication over an AC-coupled 4-wire lead between active implantable devices. The target application requires a single Chest Device be connected to a Brain Implant consisting of multiple identical optrodes that record neural activity and provide closed loop optical stimulation. The interface is integrated within each optrode SoC allowing full-duplex and fully-differential communication based on Manchester encoding. The system features a head-to-chest uplink data rate (1.6 Mbps) that is higher than that of the chest-to-head downlink (100kbps) superimposed on a power carrier. On-chip power management provides an unregulated 5 V DC supply with up to 2.5 mA output current for stimulation, and a regulated 3.3 V with 60 dB PSRR for recording and logic circuits. The circuit has been implemented in a 0.35 μm CMOS technology, occupying 1.4 mm 2 silicon area, and requiring a 62.2 μA average current consumption.

Conference paper

Williams I, Rapeaux A, Liu Y, Luan S, Constandinou TGet al., 2017, A 32-channel bidirectional neural/EMG interface with on-chip spike detection for sensorimotor feedback, IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 528-531

This paper presents a novel 32-channel bidirectional neural interface, capable of high voltage stimulation and low power, low-noise neural recording. Current-controlled biphasic pulses are output with a voltage compliance of 9.25V, user configurable amplitude (max. 315 uA) & phase duration (max. 2 ms). The low-voltage recording amplifiers consume 23 uW per channel with programmable gain between 225 - 4725. Signals are10-bit sampled at 16 kHz. Data rates are reduced by granular control of active recording channels, spike detection and event-driven communication, and repeatable multi-pulse stimulation configurations.

Conference paper

Luan S, Liu Y, Williams I, Constandinou TGet al., 2017, An Event-Driven SoC for Neural Recording, IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 404-407

This paper presents a novel 64-channel ultra-low power/low noise neural recording System-on-Chip (SoC) featuring a highly reconfigurable Analogue Front-End (AFE) and block-selectable data-driven output. This allows a tunable bandwidth/sampling rate for extracting Local Field Potentials (LFPs)and/or Extracellular Action Potentials (EAPs). Realtime spike detection utilises a dual polarity simple threshold to enable an event driven output for neural spikes (16-sample window). The 64-channels are organised into 16 sets of 4-channel recording blocks, with each block having a dedicated 10-bit SAR ADC that is time division multiplexed among the 4 channels. Eachchannel can be individually powered down and configured for bandwidth, gain and detection threshold. The output can thus combine continuous-streaming and event-driven data packets with the system configured as SPI slave. The SoC is implemented in a commercially-available 0.35u m CMOS technology occupying a silicon area of 19.1mm^2 (0.3mm^2 gross per channel) and requiring 32uW/channel power consumption (AFE only).

Conference paper

Zhao H, Dehkhoda F, Ramezani R, Sokolov D, Constandinou TG, Liu Y, Degenaar Pet al., 2016, A CMOS-Based Neural Implantable Optrode for Optogenetic Stimulation and Electrical Recording, IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 286-289

This paper presents a novel integrated optrode for simultaneous optical stimulation and electrical recording for closed -loop optogenetic neuro-prosthetic applications. The design has been implemented in a commercially available 0.35μm CMOS process. The system includes circuits for controlling the optical stimulations; recording local field potentials (LFPs); and onboard diagnostics. The neural interface has two clusters of stimulation and recording sites. Each stimulation site has a bonding point for connecting a micro light emitting diode (μLED) to deliver light to the targeted area of brain tissue. Each recording site is designed to be post-processed with electrode materials to provide monitoring ofneural activity. On-chip diagnostic sensing has been included to provide real-time diagnostics for post-implantation and during normal operation.

Conference paper

Ramezani R, Dehkhoda F, Soltan A, Degenaar P, Liu Y, Constandinou TGet al., 2016, An optrode with built-in self-diagnostic and fracture sensor for cortical brain stimulation, IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 392-395

This paper proposes a self-diagnostic subsystem for a new generation of brain implants with active electronics. The primary objective of such probes is to deliver optical pulses to optogenetic tissue and record the subsequent activity, but lifetime is currently unknown. Our proposed circuits aim to increase the safety of implanting active electronic probes into human brain tissue. Therefore, prolonging the lifetime of the implant and reducing the risks to the patient. The self-diagnostic circuit will examine the optical emitter against any abnormality or malfunctioning. The fracture sensor examinesthe optrode against any rapture or insertion breakage. The optrode including our diagnostic subsystem and fracture sensor has been designed and successfully simulated at 350nm AMS technology node and sent for manufacture.

Conference paper

Liu Y, Pereira J, Constandinou TG, 2016, Clockless Continuous-Time Neural Spike Sorting: Method, Implementation and Evaluation, IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 538-541

In this paper, we present a new method for neuralspike sorting based on Continuous Time (CT) signal processing.A set of CT based features are proposed and extracted fromCT sampled pulses, and a complete event-driven spike sortingalgorithm that performs classification based on these features isdeveloped. Compared to conventional methods for spike sorting,the hardware implementation of the proposed method does notrequire any synchronisation clock for logic circuits, and thusits power consumption depend solely on the spike activity. Thishas been implemented using a variable quantisation step CTanalogue to digital converter (ADC) with custom digital logicthat is driven by level crossing events. Simulation results usingsynthetic neural data shows a comparable accuracy comparedto template matching (TM) and Principle Components Analysis(PCA) based discrete sampled classification.

Conference paper

Dehkhoda F, Soltan A, Ramezani R, Zhao H, Liu Y, Constandinou TG, Degenaar Pet al., 2015, Smart Optrode for Neural Stimulation and Sensing, 2015 IEEE Sensors Conference, Publisher: IEEE, Pages: 1-4

Implantable neuro-prosthetics considerable clinical benefit to a range of neurological conditions. Optogenetics is a particular recent interest which utilizes high radiance light for photo-activation of genetic cells. This can provide improved biocompatibility and neural targeting over electrical stimuli. To date the primary optical delivery method in tissue for optogenetics has been via optic fibre which makes large scale multiplexing difficult. An alternative approach is to incorporate optical micro-emitters directly on implantable probes but this still requires electrical multiplexing. In this work, we demonstrate a fully active optoelectronic probe utilizing industry standard 0.35μm CMOS technology, capable of both light delivery and electrical recording. The incorporation of electronic circuits onto the device further allows us to incorporate smart sensors to determine diagnostic state to explore long term viability during chronic implantation.

Conference paper

Barsakcioglu D, Liu Y, Bhunjun P, Navajas J, Eftekhar A, Jackson A, Quian Quiroga R, Constandinou TGet al., 2014, An Analogue Front-End Model for Developing Neural Spike Sorting Systems, IEEE Transactions on Biomedical Circuits and Systems, Vol: 8, Pages: 216-227

Journal article

Reverter F, Prodromakis T, Liu Y, Georgiou P, Nikolic K, Constandinou TGet al., 2014, Design Considerations for a CMOS Lab-on-Chip Microheater Array to Facilitate the in vitro Thermal Stimulation of Neurons, IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 630-633

Conference paper

Hu Y, Liu Y, Toumazou C, Georgiou Pet al., 2012, A CMOS architecture allowing parallel DNA comparison for on-chip assembly, IEEE International Symposium on Circuits and Systems, Publisher: IEEE, Pages: 1544-1547, ISSN: 0271-4302

Conference paper

Sohbati M, Liu Y, Georgiou P, Toumazou Cet al., 2012, An ISFET design methodology incorporating CMOS passivation, Pages: 65-68

Conference paper

Wang K, Liu Y, Toumazou C, Georgiou Pet al., 2012, A TDC based ISFET readout for large-scale chemical sensing systems, Pages: 176-179

Conference paper

Liu Y, Georgiou P, Prodromakis T, Constandinou TG, Toumazou Cet al., 2011, An Extended CMOS ISFET Model Incorporating the Physical Design Geometry and the Effects on Performance and Offset Variation, IEEE Transactions on Electron Devices, Vol: 58, Pages: 4414-4422, ISSN: 0018-9383

This paper presents an extended model for theCMOS-based Ion-Sensitive-Field-Effect-Transistor (ISFET), incorporating design parameters associated with the physicalgeometry of the device. This can, for the first time, provide a good match between calculated and measured characteristics bytaking into account the effects of non-idealities such as threshold voltage variation and sensor noise. The model is evaluated through a number of devices with varying design parameters (chemical sensing area and MOSFET dimensions) fabricated ina commercially-available 0.35μm CMOS technology. Threshold voltage, subthreshold slope, chemical sensitivity, drift and noisewere measured and compared to the simulated results. The first and second order effects are analysed in detail and it is shown that the sensors’ performance was in agreement with the proposed model.

Journal article

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