Publications
45 results found
Ghoreishizadeh S, Haci D, Liu Y, et al., 2017, A 4-wire interface SoC for shared multi-implant power transfer and full-duplex communication, IEEE Latin American symposium on Circuits and Systems (LASCAS), Publisher: IEEE, Pages: 49-52, ISSN: 2473-4667
This paper describes a novel system for recovering power and providing full-duplex communication over an AC-coupled 4-wire lead between active implantable devices. The target application requires a single Chest Device be connected to a Brain Implant consisting of multiple identical optrodes that record neural activity and provide closed loop optical stimulation. The interface is integrated within each optrode SoC allowing full-duplex and fully-differential communication based on Manchester encoding. The system features a head-to-chest uplink data rate (1.6 Mbps) that is higher than that of the chest-to-head downlink (100kbps) superimposed on a power carrier. On-chip power management provides an unregulated 5 V DC supply with up to 2.5 mA output current for stimulation, and a regulated 3.3 V with 60 dB PSRR for recording and logic circuits. The circuit has been implemented in a 0.35 μm CMOS technology, occupying 1.4 mm 2 silicon area, and requiring a 62.2 μA average current consumption.
Williams I, Rapeaux A, Liu Y, et al., 2017, A 32-channel bidirectional neural/EMG interface with on-chip spike detection for sensorimotor feedback, IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 528-531
This paper presents a novel 32-channel bidirectional neural interface, capable of high voltage stimulation and low power, low-noise neural recording. Current-controlled biphasic pulses are output with a voltage compliance of 9.25V, user configurable amplitude (max. 315 uA) & phase duration (max. 2 ms). The low-voltage recording amplifiers consume 23 uW per channel with programmable gain between 225 - 4725. Signals are10-bit sampled at 16 kHz. Data rates are reduced by granular control of active recording channels, spike detection and event-driven communication, and repeatable multi-pulse stimulation configurations.
Luan S, Liu Y, Williams I, et al., 2017, An Event-Driven SoC for Neural Recording, IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 404-407
This paper presents a novel 64-channel ultra-low power/low noise neural recording System-on-Chip (SoC) featuring a highly reconfigurable Analogue Front-End (AFE) and block-selectable data-driven output. This allows a tunable bandwidth/sampling rate for extracting Local Field Potentials (LFPs)and/or Extracellular Action Potentials (EAPs). Realtime spike detection utilises a dual polarity simple threshold to enable an event driven output for neural spikes (16-sample window). The 64-channels are organised into 16 sets of 4-channel recording blocks, with each block having a dedicated 10-bit SAR ADC that is time division multiplexed among the 4 channels. Eachchannel can be individually powered down and configured for bandwidth, gain and detection threshold. The output can thus combine continuous-streaming and event-driven data packets with the system configured as SPI slave. The SoC is implemented in a commercially-available 0.35u m CMOS technology occupying a silicon area of 19.1mm^2 (0.3mm^2 gross per channel) and requiring 32uW/channel power consumption (AFE only).
Zhao H, Dehkhoda F, Ramezani R, et al., 2016, A CMOS-Based Neural Implantable Optrode for Optogenetic Stimulation and Electrical Recording, IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 286-289
This paper presents a novel integrated optrode for simultaneous optical stimulation and electrical recording for closed -loop optogenetic neuro-prosthetic applications. The design has been implemented in a commercially available 0.35μm CMOS process. The system includes circuits for controlling the optical stimulations; recording local field potentials (LFPs); and onboard diagnostics. The neural interface has two clusters of stimulation and recording sites. Each stimulation site has a bonding point for connecting a micro light emitting diode (μLED) to deliver light to the targeted area of brain tissue. Each recording site is designed to be post-processed with electrode materials to provide monitoring ofneural activity. On-chip diagnostic sensing has been included to provide real-time diagnostics for post-implantation and during normal operation.
Ramezani R, Dehkhoda F, Soltan A, et al., 2016, An optrode with built-in self-diagnostic and fracture sensor for cortical brain stimulation, IEEE Biomedical Circuits and Systems (BioCAS) Conference, Publisher: IEEE, Pages: 392-395
This paper proposes a self-diagnostic subsystem for a new generation of brain implants with active electronics. The primary objective of such probes is to deliver optical pulses to optogenetic tissue and record the subsequent activity, but lifetime is currently unknown. Our proposed circuits aim to increase the safety of implanting active electronic probes into human brain tissue. Therefore, prolonging the lifetime of the implant and reducing the risks to the patient. The self-diagnostic circuit will examine the optical emitter against any abnormality or malfunctioning. The fracture sensor examinesthe optrode against any rapture or insertion breakage. The optrode including our diagnostic subsystem and fracture sensor has been designed and successfully simulated at 350nm AMS technology node and sent for manufacture.
Liu Y, Pereira J, Constandinou TG, 2016, Clockless Continuous-Time Neural Spike Sorting: Method, Implementation and Evaluation, IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 538-541
In this paper, we present a new method for neuralspike sorting based on Continuous Time (CT) signal processing.A set of CT based features are proposed and extracted fromCT sampled pulses, and a complete event-driven spike sortingalgorithm that performs classification based on these features isdeveloped. Compared to conventional methods for spike sorting,the hardware implementation of the proposed method does notrequire any synchronisation clock for logic circuits, and thusits power consumption depend solely on the spike activity. Thishas been implemented using a variable quantisation step CTanalogue to digital converter (ADC) with custom digital logicthat is driven by level crossing events. Simulation results usingsynthetic neural data shows a comparable accuracy comparedto template matching (TM) and Principle Components Analysis(PCA) based discrete sampled classification.
Dehkhoda F, Soltan A, Ramezani R, et al., 2015, Smart Optrode for Neural Stimulation and Sensing, 2015 IEEE Sensors Conference, Publisher: IEEE, Pages: 1-4
Implantable neuro-prosthetics considerable clinical benefit to a range of neurological conditions. Optogenetics is a particular recent interest which utilizes high radiance light for photo-activation of genetic cells. This can provide improved biocompatibility and neural targeting over electrical stimuli. To date the primary optical delivery method in tissue for optogenetics has been via optic fibre which makes large scale multiplexing difficult. An alternative approach is to incorporate optical micro-emitters directly on implantable probes but this still requires electrical multiplexing. In this work, we demonstrate a fully active optoelectronic probe utilizing industry standard 0.35μm CMOS technology, capable of both light delivery and electrical recording. The incorporation of electronic circuits onto the device further allows us to incorporate smart sensors to determine diagnostic state to explore long term viability during chronic implantation.
Reverter F, Prodromakis T, Liu Y, et al., 2014, Design Considerations for a CMOS Lab-on-Chip Microheater Array to Facilitate the in vitro Thermal Stimulation of Neurons, IEEE International Symposium on Circuits and Systems (ISCAS), Publisher: IEEE, Pages: 630-633
Barsakcioglu D, Liu Y, Bhunjun P, et al., 2014, An Analogue Front-End Model for Developing Neural Spike Sorting Systems, IEEE Transactions on Biomedical Circuits and Systems, Vol: 8, Pages: 216-227
Hu Y, Liu Y, Toumazou C, et al., 2012, A CMOS architecture allowing parallel DNA comparison for on-chip assembly, IEEE International Symposium on Circuits and Systems, Publisher: IEEE, Pages: 1544-1547, ISSN: 0271-4302
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Sohbati M, Liu Y, Georgiou P, et al., 2012, An ISFET design methodology incorporating CMOS passivation, Pages: 65-68
Wang K, Liu Y, Toumazou C, et al., 2012, A TDC based ISFET readout for large-scale chemical sensing systems, Pages: 176-179
Liu Y, Georgiou P, Prodromakis T, et al., 2011, An Extended CMOS ISFET Model Incorporating the Physical Design Geometry and the Effects on Performance and Offset Variation, IEEE Transactions on Electron Devices, Vol: 58, Pages: 4414-4422, ISSN: 0018-9383
This paper presents an extended model for theCMOS-based Ion-Sensitive-Field-Effect-Transistor (ISFET), incorporating design parameters associated with the physicalgeometry of the device. This can, for the first time, provide a good match between calculated and measured characteristics bytaking into account the effects of non-idealities such as threshold voltage variation and sensor noise. The model is evaluated through a number of devices with varying design parameters (chemical sensing area and MOSFET dimensions) fabricated ina commercially-available 0.35μm CMOS technology. Threshold voltage, subthreshold slope, chemical sensitivity, drift and noisewere measured and compared to the simulated results. The first and second order effects are analysed in detail and it is shown that the sensors’ performance was in agreement with the proposed model.
Prodromakis T, Liu Y, Toumazou C, 2011, A Low-Cost Disposable Chemical Sensing Platform Based on Discrete Components, IEEE Electron Device Letters, Vol: 32, Pages: 417-419
A method of fabricating low-cost chemical sens- ing platforms is presented. The device utilizes a discrete metal–oxide–semiconductor field-effect transistor to detect ionic concentrations in electrolytes, with particular emphasis to pH. Measured results indicate a chemical sensitivity of 36.5 mV/pH, while the device exhibits low-leakage currents (in picoamperes) and a drift of 9 mV/h. The proposed technique has a great potential for disposable implementations, while the sensing selectivity of the device can be easily altered, resulting into a versatile platform.
Prodromakis T, Liu Y, Constandinou TG, et al., 2010, Exploiting CMOS Technology to Enhance the Performance of ISFET Sensors, IEEE Electron Device Letters, Vol: 31, Pages: 1053-1055, ISSN: 0741-3106
This paper presents a novel method for fabricating ISFET devices in unmodified CMOS technologies. Conventional CMOS ISFETs utilise the protective passivation coating as the sensing membrane, with the sensed potential being coupled down to the floating MOS gate via a stack of conducting and insulating layers. The proposed structure minimises the use of these layers by exploiting the passivation opening mask, normally intended for bondpad openings. Parasitic effects such as reduced transconductance and trapped charge within the floating gate structure are minimised, resulting in a lower VT and improved chemical transconductance efficiency. Other characteristics including chemical sensitivity, reference leakage current and noise power are at comparable levels with conventional CMOS-based ISFET devices.
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