138 results found
Durrani Z, Abualnaja F, Jones M, 2022, Room temperature Szilard cycle and entropy exchange at the Landauer limit in a dopant atom double quantum dot silicon transistor, JOURNAL OF PHYSICS D-APPLIED PHYSICS, Vol: 55, ISSN: 0022-3727
Abualnaja F, He W, Durrani Z, et al., 2021, Room-temperature double quantum dot for investigating Maxwell’s Demon, Micro and Nano Engineering (MNE) 2021 Trieste
Abualnaja F, Wang C, Veigang-Radulescu V-P, et al., 2019, Room-temperature measurement of electrostatically coupled, dopant-atom double quantum dots in point-contact transistors, Physical Review Applied, Vol: 12, Pages: 1-11, ISSN: 2331-7019
The reduction of nanoelectronic devices to sub-10 nm sizes raises the prospect of electronics at the atomic scale, while also facilitating studies on nanoscale device physics. Single-atom transistors, where the current-switching element is formed by one atom and the information packet size is reduced to one electron, can create electronic switches scaled to their ultimate physical limits. Hitherto, single-atom transistor operation has been limited to low temperatures due to shallow quantum wells, which inhibit room-temperature nanoelectronic applications. Furthermore, the interaction between multiple single-atom elements at room temperature has yet to be demonstrated. Here, we show that quantum interactions between P dopants in Si/SiO2/Si single-atom transistors lead to room-temperature double quantum dot behavior. Hexagonal regions of charge stability and gate-controlled tunnel coupling between P atoms are observed at room temperature. Image processing is used to help reduce observer bias in data analysis. Single-electron device simulation is used to investigate evolution of the charge-stability region with varying capacitance and resistance. In combination with extracted tunnel capacitances and resistances, this allows experimental trends to be reproduced and provides information on the dopant-atom arrangement.
Durrani Z, Abualnaja F, He W, et al., 2019, Room-temperature single and double quantum dot transistors using dopant atoms, 2nd International Workshop on 2D Materials and Quantum Effect Devices
Abualnaja F, Wang C, Veigang-Radulescu V-P, et al., 2019, Electrostatically-coupled dopant atom quantum dot transistor measurement at room-temperature, Micro and Nano Engineering (MNE) 2019, Rhodes
Rawlings CD, Ryu YK, Rüegg M, et al., 2018, Fast turnaround fabrication of silicon point-contact quantum-dot transistors using combined thermal scanning probe lithography and laser writing., Nanotechnology, Vol: 29, ISSN: 0957-4484
The fabrication of high-performance solid-state silicon quantum-devices requires high resolution patterning with minimal substrate damage. We have fabricated room temperature single-electron transistors (SETs) based on point-contact tunnel junctions using a hybrid lithography tool capable of both high resolution thermal scanning probe lithography and high throughput direct laser writing. The best focal z-position and the offset of the tip- and the laser-writing positions were determined in-situ with the scanning probe. We demonstrate < 100 nm precision in the registration between the high resolution and high throughput lithographies. The SET devices were fabricated on degenerately doped n-type > 1020/cm3 silicon on insulator (SOI) chips using a CMOS compatible geometric oxidation process. The characteristics of the three devices investigated were dominated by the presence of Si nanocrystals or phosphorous atoms embedded within the SiO2, forming quantum dots (QDs). The small size and strong localisation of electrons on the QDs facilitated SET operation even at room temperature. Temperature measurements showed that in the range 300 K > T > ~100 K, the current flow was thermally activated but at < 100 K, it was dominated by tunnelling.
Durrani Z, Jones M, Abualnaja F, et al., 2018, Room-temperature single dopant atom quantum dot transistors in silicon, formed by field-emission scanning probe lithography, Journal of Applied Physics, Vol: 124, ISSN: 0021-8979
Electrical operation of room-temperature (RT) single dopant atom quantum dot (QD) transistors, based on phosphorous atoms isolated within nanoscale SiO2 tunnel barriers, is presented. In contrast to single dopant transistors in silicon, where the QD potential well is shallow and device operation limited to cryogenic temperature, here, a deep (∼2 eV) potential well allows electron confinement at RT. Our transistors use ∼10 nm size scale Si/SiO2/Si point-contact tunnel junctions, defined by scanning probe lithography and geometric oxidation. “Coulomb diamond” charge stability plots are measured at 290 K, with QD addition energy ∼0.3 eV. Theoretical simulation gives a QD size of similar order to the phosphorous atom separation ∼2 nm. Extraction of energy states predicts an anharmonic QD potential, fitted using a Morse oscillator-like potential. The results extend single-atom transistor operation to RT, enable tunneling spectroscopy of impurity atoms in insulators, and allow the energy landscape for P atoms in SiO2 to be determined.
Durrani Z, Abualnaja F, Jones M, 2018, Beyond-CMOS electronics: Semiconductor devices at the sub-10 nm to atomic scale, International Workshop on 2D Materials and Quantum Effect Devices 12-14 November, 2018
Abualnaja F, Durrani Z, Jones M, et al., 2018, Room Temperature Quantum Dot Transistors Using Field‐Emission Scanning Probe Lithography, Micro and Nano Engineering (MNE) 2018, Copenhagen
Lenk C, Hofmann M, Lenk S, et al., 2018, Nanofabrication by field-emission scanning probe lithography and cryogenic plasma etching, Microelectronic Engineering Vol. 192, p77-82 (2018)
Rangelow IW, Lenk C, Hofmann M, et al., 2018, Field-Emission Scanning Probe Lithography with self-actuating and self-sensing cantilevers for devices with single digit nanometer dimensions, Conference on Novel Patterning Technologies, Publisher: SPIE-INT SOC OPTICAL ENGINEERING, ISSN: 0277-786X
Durrani ZAK, Jones ME, Wang C, et al., 2017, Electron transport and room temperature single-electron charging in 10nm scale PtC nanostructures formed by electron beam induced deposition, NANOTECHNOLOGY, Vol: 28, ISSN: 0957-4484
Holz M, Guliyev E, Kaestner M, et al., 2017, 6” Wafer scale field-emission scanning probe lithography (FE-SPL) and fast AFM tool employing active cantilever for mix&match single-digit nanolithography, Micro and Nano Engineering (MNE) 2017, Braga
Yu Kyoung R, Rawlings C, Spieser M, et al., 2017, Fabrication of high resolution nano-devices by thermal scanning probe lithography, Micro and Nano Engineering (MNE) 2017, Braga
Durrani Z, Jones M, Liu D, et al., 2017, Room temperature double quantum dots in silicon point-contact SETs, Micro and Nano Engineering (MNE) 2017, Braga
Lenk C, Kaestner M, Krivoshapkina Y, et al., 2017, Room-temperature single electron transistors fabricated by field-emission scanning probe lithography and cryogenic plasma etching, Micro and Nano Engineering (MNE) 2017, Braga
Durrani ZAK, Jones ME, Wang C, et al., 2017, Excited states and quantum confinement in room temperature few nanometre scale silicon single electron transistors, Nanotechnology, Vol: 28, Pages: 1-11, ISSN: 0957-4484
Single nanometre scale quantum dots (QDs) have significant potential for many 'beyond CMOS' nanoelectronics and quantum computation applications. The fabrication and measurement of few nanometre silicon point-contact QD single-electron transistors are reported, which both operate at room temperature (RT) and are fabricated using standard processes. By combining thin silicon-on-insulator wafers, specific device geometry, and controlled oxidation, <10 nm nanoscale point-contact channels are defined. In this limit of the point-contact approach, ultra-small, few nanometre scale QDs are formed, enabling RT measurement of the full QD characteristics, including excited states to be made. A remarkably large QD electron addition energy ~0.8 eV, and a quantum confinement energy ~0.3 eV, are observed, implying a QD only ~1.6 nm in size. In measurements of 19 RT devices, the extracted QD radius lies within a narrow band, from 0.8 to 2.35 nm, emphasising the single-nanometre scale of the QDs. These results demonstrate that with careful control, 'beyond CMOS' RT QD transistors can be produced using current 'conventional' semiconductor device fabrication techniques.
Rangelow IW, Ahmad A, Ivanov T, et al., 2016, Pattern-generation and pattern-transfer for single-digit nano devices, Journal of Vacuum Science and Technology B, Vol: 34, ISSN: 2166-2746
Single-electron devices operating at room temperature require sub-5 nm quantum dots having tunnel junctionsof comparable dimensions. Further development in nanoelectronics depends on the capability to generatemesoscopic structures and interfacing these with complementary metal–oxide–semiconductordevices in a single system. The authors employ a combination of two novel methods of fabricating roomtemperature silicon single-electron transistors (SETs), Fowler–Nordheim scanning probe lithography (F-NSPL) with active cantilevers and cryogenic reactive ion etching followed by pattern-dependent oxidation.The F-N SPL employs a low energy electron exposure of 5–10 nm thick high-resolution molecular resist(Calixarene) resulting in single nanodigit lithographic performance [Rangelow et al., Proc. SPIE 7637,76370V (2010)]. The followed step of pattern transfer into silicon becomes very challenging because ofthe extremely low resist thickness, which limits the etching depth. The authors developed a computer simulationcode to simulate the reactive ion etching at cryogenic temperatures (!120 "C). In this article, theauthors present the alliance of all these technologies used for the manufacturing of SETs capable to operateat room temperatures.
Liu D, Wang C, Jones M, et al., 2016, Fabricating single electron devices in silicon for room temperature operation using electron beam lithography and geometric oxidation, Micro and Nano Engineering (MNE) 2016, Vienna
Llobet J, Krali E, Wang C, et al., 2015, Resonant tunnelling features in a suspended silicon nanowire single-hole transistor, Applied Physics Letters, Vol: 107, ISSN: 1077-3118
Suspended silicon nanowires have significant potential for a broad spectrum of device applications. A suspended p-type Si nanowire incorporating Si nanocrystalquantum dots has been used to form a single-hole transistor.Transistor fabrication uses a novel and rapid process, based on focused gallium ion beam exposure and anisotropic wet etching, generating <10 nm nanocrystals inside suspended Si nanowires. Electrical characteristics at 10 K show Coulomb diamonds with charging energy ∼27 meV, associated with a single dominant nanocrystal.Resonant tunnelling features with energy spacing ∼10 meV are observed, parallel to both diamond edges. These may be associated either with excited states or hole–acoustic phonon interactions, in the nanocrystal. In the latter case, the energy spacing corresponds well with reported Raman spectroscopy results and phonon spectra calculations.
Wang C, Jones ME, Durrani ZAK, 2015, Single-electron and quantum confinement limits in length-scaled silicon nanowires, Nanotechnology, Vol: 26, ISSN: 0957-4484
Quantum-effects will play an important role in both future CMOS and 'beyond CMOS' technologies. By comparing single-electron transistors formed in un-patterned, uniform-width silicon nanowire (SiNW) devices with core widths from ~5–40 nm, and gated lengths of 1 μm and ~50 nm, we show conditions under which these effects become significant. Coulomb blockade drain–source current–voltage characteristics, and single-electron current oscillations with gate voltage have been observed at room temperature. Detailed electrical characteristics have been measured from 8–300 K. We show that while shortening the nanowire gate length to 50 nm reduces the likelihood of quantum dots to only a few, it increases their influence on the electrical characteristics. This highlights explicitly both the significance of quantum effects for understanding the electrical performance of nominally 'classical' SiNW devices and also their potential for new quantum effect 'beyond CMOS' devices.
Krali E, Llobet J, Wang C, et al., 2015, Fabrication of a suspended silicon nanowire single hole transistor by focused ion beam implantation, Micro and Nano Engineering (MNE) 2015, The Hague
Durrani Z, 2015, Sub-10 nm device development within the SNM Project, Micro and Nano Engineering (MNE) 2015, The Hague
Rasool K, Rafiq MA, Ahmad M, et al., 2015, Charge injection and trapping in TiO2 nanoparticles decorated silicon nanowires arrays, Applied Physics Letters, Vol: 106, ISSN: 1077-3118
We investigate carrier transport properties of silicon nanowire (SiNW) arrays decorated with TiO2nanoparticles (NPs). Ohmic conduction was dominant at lower voltages and space charge limitedcurrent with and without traps was observed at higher voltages. Mott’s 3D variable range hopingmechanism was found to be dominant at lower temperatures. The minimum hopping distance(Rmin) for n and p-SiNWs/TiO2 NPs devices was 1.5 nm and 0.68 nm, respectively, at 77 K. Thedecrease in the value of Rmin can be attributed to higher carrier mobility in p-SiNWs/TiO2 NPs thanthat of n-SiNWs/TiO2 NPs hybrid device.
Zadeh YH, Durrani ZAK, 2014, Inelastic electron tunneling spectroscopy for molecular detection, Journal of Vacuum Science and Technology B, Vol: 32, ISSN: 2166-2746
Inelastic electron tunneling spectroscopy (IETS) [R. C. Jaklevic and J. Lambe, Phys. Rev. Lett.17, 1139 (1966); R. G. Keil et al., Appl. Spectrosc. 30, 1 (1976); K. W. Hipps and U. Mazur, J.Phys. Chem. 97, 7803 (1993); U. Mazur et al., Anal. Chem. 64, 1845 (1992); P. K. Hansma,Tunneling Spectroscopy (Plenum, New York, 1982)] measurements are performed on Sinanowire (NW)/SiO2/Al NW tunnel junctions. The tunnel junction area is 50 120 nm andtunneling occurs across a 10 nm thick SiO2 layer. IETS measurements are performed at 300 K forammonium hydroxide (NH4OH), acetic acid (CH3COOH), and propionic acid (C3H6O2)molecules. The I–V, dI/dV–V, and d2I/dV2–V characteristics of the tunnel junction aremeasured before and after the adsorption of molecules on the junction using vapor treatment orimmersion. Peaks can be observed in the d2I/dV2–V characteristics in all the cases followingmolecules adsorption. These peaks may be attributed to vibrational modes of N–H and C–Hbonds.
Wang C, Jones M, Durrani Z, 2014, Nanowire single electron devices defined by EBL, Micro and Nano Engineering (MNE) 2014, Lausanne
Krali E, Fobelets K, Durrani Z, 2014, Seebeck coefficient in Si nanowires and single-electron effects, Mico and Nano Engineering (MNE) 2014, Lausanne
Rasool K, Rafiq MA, Durrani ZAK, 2014, Tailoring transport and dielectric properties by surface passivation of silicon nanowires with Polyacrylic acid/TiO2 nanoparticles composite, MICROELECTRONIC ENGINEERING, Vol: 119, Pages: 141-145, ISSN: 0167-9317
Durrani ZAK, 2014, Seebeck coefficient of one electron, Journal of Applied Physics, Vol: 115, ISSN: 0021-8979
The Seebeck coefficient of one electron, driven thermally into a semiconductor single-electron box, is investigated theoretically. With a finite temperature difference ΔT between the source and charging island, a single electron can charge the island in equilibrium, directly generating a Seebeck effect. Seebeck coefficients for small and finite ΔT are calculated and a thermally driven Coulomb staircase is predicted. Single-electron Seebeck oscillations occur with increasing ΔT, as one electron at a time charges the box. A method is proposed for experimental verification of these effects.
Krali E, Durrani ZAK, 2013, Seebeck coefficient in silicon nanowire arrays (vol 102, 143102, 2013), APPLIED PHYSICS LETTERS, Vol: 103, ISSN: 0003-6951
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