Professor Peter Y. K. Cheung

Faculty of Engineering, Dyson School of Design Engineering

Professor of Digital Systems

Contact

+44 (0)20 7594 6200p.cheung Website

Assistant

Mrs Wiesia Hsissen +44 (0)20 7594 6261

Location

910BElectrical EngineeringSouth Kensington Campus

Summary

Publications

Citation

BibTex format

@inproceedings{Sedcole:2008:10.1109/FPT.2008.4762386,
author = {Sedcole, P and Wong, JS and Cheung, PYK},
doi = {10.1109/FPT.2008.4762386},
pages = {217--224},
publisher = {IEEE},
title = {Modelling and Compensating for Clock Skew Variability in FPGAs},
url = {http://dx.doi.org/10.1109/FPT.2008.4762386},
year = {2008}
}

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RIS format (EndNote, RefMan)

TY  - CPAPER
AU  - Sedcole,P
AU  - Wong,JS
AU  - Cheung,PYK
DO  - 10.1109/FPT.2008.4762386
EP  - 224
PB  - IEEE
PY  - 2008///
SP  - 217
TI  - Modelling and Compensating for Clock Skew Variability in FPGAs
UR  - http://dx.doi.org/10.1109/FPT.2008.4762386
UR  - https://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000263224000028&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=a2bf6146997ec60c407a63945d4e92bb
ER  -

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