Publications

BibTex format

@unpublished{Leene:2019,
author = {Leene, LB and Letchumanan, S and Constandinou, TG},
publisher = {IEEE},
title = {A 68 mu W 31 kS/s Fully-Capacitive Noise-Shaping SAR ADC with 102 dB SNDR},
url = {http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000483076401181&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=1ba7043ffcc86c417c072aa74d649202},
year = {2019}
}

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RIS format (EndNote, RefMan)

TY  - UNPB
AB  - This paper presents a 17 bit analogue-to-digital converter that incorporatesmismatch and quantisation noise-shaping techniques into an energy-saving 10 bitsuccessive approximation quantiser to increase the dynamic range by another 42dB. We propose a novel fully-capacitive topology which allows for high-speedasynchronous conversion together with a background calibration scheme to reducethe oversampling requirement by 10x compared to prior-art. A 0.18 um CMOStechnology is used to demonstrate preliminary simulation results together withanalytic measures that optimise parameter and topology selection. The proposedsystem is able to achieve a FoMS of 183 dB for a maximum signal bandwidth of15.6 kHz while dissipating 68 uW from a 1.8 V supply. A peak SNDR of 102 dB isdemonstrated for this rate with a 0.201 mm^2 area requirement.
AU  - Leene,LB
AU  - Letchumanan,S
AU  - Constandinou,TG
PB  - IEEE
PY  - 2019///
TI  - A 68 mu W 31 kS/s Fully-Capacitive Noise-Shaping SAR ADC with 102 dB SNDR
UR  - http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000483076401181&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=1ba7043ffcc86c417c072aa74d649202
UR  - http://hdl.handle.net/10044/1/72247
ER  -

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Professor Timothy Constandinou

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