Imperial College London

Professor Peter Y. K. Cheung

Faculty of EngineeringDyson School of Design Engineering

Head of the Dyson School of Design Engineering
 
 
 
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Contact

 

+44 (0)20 7594 6200p.cheung Website

 
 
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Assistant

 

Mrs Wiesia Hsissen +44 (0)20 7594 6261

 
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Location

 

910BElectrical EngineeringSouth Kensington Campus

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Summary

 

Publications

Citation

BibTex format

@inproceedings{Zhao:2019,
author = {Zhao, Y and Gao, X and Liu, J and Wang, E and Mullins, R and Cheung, P and Constantinides, G and Xu, C-Z},
publisher = {IEEE},
title = {Automatic generation of multi-precision multi-arithmetic CNN accelerators for FPGAs},
url = {http://hdl.handle.net/10044/1/75446},
year = {2019}
}

RIS format (EndNote, RefMan)

TY  - CPAPER
AB - Modern deep Convolutional Neural Networks (CNNs) are computationally demanding, yet real applications often require high throughput and low latency. To help tackle these problems, we propose Tomato, a framework designed to automate the process of generating efficient CNN accelerators. The generated design is pipelined and each convolution layer uses different arithmetics at various precisions. Using Tomato, we showcase state-of-the-art multi-precision multi-arithmetic networks, including MobileNet-V1, running on FPGAs. To our knowledge, this is the first multi-precision multi-arithmetic auto-generation framework for CNNs. In software, Tomato fine-tunes pretrained networks to use a mixture of short powers-of-2 and fixed-point weights with a minimal loss in classification accuracy. The fine-tuned parameters are combined with the templated hardware designs to automatically produce efficient inference circuits in FPGAs. We demonstrate how our approach significantly reduces model sizes and computation complexities, and permits us to pack a complete ImageNet network onto a single FPGA without accessing off-chip memories for the first time. Furthermore, we show how Tomato produces implementations of networks with various sizes running on single or multiple FPGAs. To the best of our knowledge, our automatically generated accelerators outperform closest FPGA-based competitors by at least 2-4x for lantency and throughput; the generated accelerator runs ImageNet classification at a rate of more than 3000 frames per second.
AU - Zhao,Y
AU - Gao,X
AU - Liu,J
AU - Wang,E
AU - Mullins,R
AU - Cheung,P
AU - Constantinides,G
AU - Xu,C-Z
PB - IEEE
PY - 2019///
TI - Automatic generation of multi-precision multi-arithmetic CNN accelerators for FPGAs
UR - http://hdl.handle.net/10044/1/75446
ER -